DR. HAU THI NGUYEN, M.D.
Medical Practice at Bascom Ave, San Jose, CA

2003005, Mar 27, 2003

Jun 6, 2002

10/165548

Luu Nguyen - Sunnyvale CA, US
Ken Pham - San Jose CA, US
Peter Deane - Los Altos CA, US
William Mazotti - San Martin CA, US
Bruce Roberts - San Jose CA, US
Hau Nguyen - San Jose CA, US
John Briant - Cambridge, GB
Roger Clarke - Cambridge, GB
Michael Nelson - Cambridge, GB
Janet Townsend - Fulbourn, GB

National Semiconductor Corporation - Santa Clara CA

H01L029/768, H01L027/148

257/678000, 257/222000

The techniques of the present invention are directed towards setting a photonic device into a groove of a substrate, which is then attached to the chip sub-assembly in a way that the resulting optoelectronic package has a low profile and the interconnects between the photonic device and the semiconductor chip are short. The technique involves partially etching a groove in a substrate to allow for positioning of a photonic device within the groove. The photonic device is connected to the chip sub-assembly through interconnects that extend through the thickness of the substrate. The photonic devices are placed on their sides so that the active facets are perpendicular to the main axis of the chip sub-assembly. In this configuration, the optical fibers can be positioned parallel to the CSA top surface, ensuring a low module profile in the process.

7812462, Oct 12, 2010

Nov 4, 2008

12/264814

Stephen Gee - Danville CA, US
Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/485

257786, 257E2302

The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction between the die and solder bump, which may reduce voiding and localized heating.

2012032, Dec 27, 2012

Jun 24, 2011

13/168701

Tao FENG - Santa Clara CA, US
Will K. WONG - Belmont CA, US
Ashok S. PRABHU - San Jose CA, US
Hau T. NGUYEN - San Jose CA, US
Anindya PODDAR - Sunnyvale CA, US

NATIONAL SEMICONDUCTOR CORPORATION - Santa Clara CA

H01L 23/498, H01L 21/50

257737, 438107, 438113, 438109, 438108, 257E21499, 257E23068

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

7755200, Jul 13, 2010

Sep 15, 2008

12/210920

Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/48

257773, 257738, 257739, 257772, 257779, 257780

The present invention relates to methods and arrangements for forming a solder joint connection. One embodiment involves an improved solder ball. The solder ball includes a perforated, metallic shell with an internal opening. Solder material encases the shell and fills its internal opening. The solder ball may be applied to an electrical device, such as an integrated circuit die, to form a solder bump on the device. The solder bump in turn can be used to form an improved solder joint connection between the device and a suitable substrate, such as a printed circuit board. In some applications, a solder joint connection is formed without requiring the application of additional solder material to the surface of the substrate. The present invention also includes different solder bump arrangements and methods for using such arrangements to form solder joint connections between devices and substrates.

7629246, Dec 8, 2009

Aug 30, 2007

11/897971

Viraj Patwardhan - Milpitas CA, US
Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/44

438613, 438615, 257E21508

A Micro SMDxt package is provided that configured for mounting to a circuit board. The SMDxt package includes a silicon-based IC having an array of contact pads on one side of thereof, and a die electrically attached to the silicon-based IC. A plurality of solder balls is included, each of which has a polymeric core surrounded by a metallic shell that in turn is surrounded by a layer of solder material. Further, each solder ball is positioned in contact with a corresponding contact pad of the package. An intertwined intermetallic fusion layer is formed through the fusion between material components of the contact pads and the solder material, via heat treatment. The intermetallic fusion extends between and from an outer surface of the metallic shell of each solder to an outer surface of a corresponding contact pad to form a high strength intermetallic solder joint therebetween.

7510908, Mar 31, 2009

Feb 1, 2005

11/050267

Hau Thanh Nguyen - San Jose CA, US
Nikhil Kelkar - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/00

438114, 438462, 438465

Disclosed is a packaged semiconductor device. The device includes a die with an active surface having a plurality of electrical contacts, a back surface located opposite the active surface, and a plurality of side surfaces. The device also includes a first light blocking protective coating that covers at least a portion of the side surfaces of the die. Also, disclosed is a semiconductor wafer including an active surface and a back surface, the active surface having a multiplicity of electrical contacts. The wafer includes a plurality of channels formed in the active surface of the wafer, the channels being arranged in a grid that effectively divide the wafer into a plurality of dice, each die having a plurality of the electrical contacts; and a light blocking filler material that fills the channels. Further, disclosed is a stamp suitable for applying a light blocking filler material into grooves on a semiconductor wafer. The stamp includes a base plate; and a multiplicity of spaced apart fins arranged in a matrix of lines that define a grid sized to match the spacing of saw streets in an associated semiconductor wafer, each line of the matrix having a series of spaced apart fins.

8389334, Mar 5, 2013

Aug 17, 2010

12/858331

Nghia T. Tu - San Jose CA, US
Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/31

438113

One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method.

7253078, Aug 7, 2007

Aug 19, 2002

10/224291

Luu T. Nguyen - Sunnyvale CA, US
Hau T. Nguyen - San Jose CA, US
Viraj A. Patwardhan - Sunnyvale CA, US
Nikhil Kelkar - San Jose CA, US
Shahram Mostafazadeh - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/44

438411

An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.

2009017, Jul 9, 2009

Jan 4, 2008

11/969704

Hau Nguyen - San Jose CA, US
Luu T. Nguyen - San Jose CA, US
Anindya Poddar - Sunnyvale CA, US

NATIONAL SEMICONDUCTOR CORPORATION - Santa Clara CA

H01L 23/488

257737, 257E23023

A semiconductor device is described. The device includes an integrated circuit die having an active surface that includes a plurality of input/output (I/O) pads. The device further includes a plurality of crack resistant structures. Each crack resistant structure is formed over an associated I/O pad and includes an associated raised portion. Each I/O pad may be bumped with solder such that a solder bump is formed over the associated crack resistant structure on the I/O pad.