HARRY LAMAR JONES, M.D.
Radiology at Medical Pkwy, Austin, TX

License number
Texas D9517
Category
Radiology
Type
Surgery
Address
Address
3901 Medical Pkwy SUITE 200, Austin, TX 78756
Phone
(512) 467-7151
(512) 467-8809 (Fax)

Personal information

See more information about HARRY LAMAR JONES at radaris.com
Name
Address
Phone
Harry Jones
514 E 34Th St, Lubbock, TX 79404
Harry Jones
5201 S Broadway Ave, Tyler, TX 75703
Harry Jones
5101 Paint Rock Ct, Fort Worth, TX 76132
Harry Jones
5103 Rolling Timbers Ct, Houston, TX 77084
Harry Jones
5136 Pond View Ln, McKinney, TX 75069

Professional information

Harry Lamar Jones Photo 1

Harry Lamar Jones, Austin TX

Specialties:
Surgeon
Address:
3901 Medical Pkwy, Austin, TX 78756
Board certifications:
American Board of Surgery Certification in Surgery


Harry Jones Photo 2

Balltape Structure For Tape Automated Bonding, Multilayer Packaging, Universal Chip Interconnection And Energy Beam Processes For Manufacturing Balltape

US Patent:
4814855, Mar 21, 1989
Filed:
Apr 29, 1986
Appl. No.:
6/857227
Inventors:
Rodney T. Hodgson - Ossining NY
Harry J. Jones - Austin TX
Peter G. Ledermann - Pleasantville NY
Timothy C. Reiley - Ridgefield CT
Paul A. Moskowitz - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H02G 1308
US Classification:
174 524
Abstract:
Automated bonding of chips to tape and formation of bonding structures on Tape Automated Bonding (TAB) packaging structures are provided with bonding balls on the ends of beams leads of the TAB tape. Also balltape bonding balls are aligned on stacked TAB sheets and bonded together to form via interconnections through stacked balltape balls in multilayer, electronic packaging structures. Interconnection structures are provided for a universal chip connection laminate which can be applied between a chip and an MLC package. Area TAB tape, which comprises a modification of TAB tape provides balltape TAB connections by means of balltape bonds to areas within the interior of a chip whose leads are bonded in a TAB tape arrangement to the Inner Lead Bonds of the area tape.


Harry Jones Photo 3

Electronic Ec For Minimizing Ec Pads

US Patent:
4746815, May 24, 1988
Filed:
Jul 3, 1986
Appl. No.:
6/881755
Inventors:
Harsaran S. Bhatia - Hopewell Junction NY
Mario E. Ecker - Poughkeepsie NY
Harry J. Jones - Austin TX
Shashi D. Malaviya - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 326, H03K 3335
US Classification:
307303
Abstract:
A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.


Harry Jones Photo 4

Dotting Circuit With Inhibit Function

US Patent:
4743781, May 10, 1988
Filed:
Jul 3, 1986
Appl. No.:
6/882058
Inventors:
Harsaran S. Bhatia - Hopewell Junction NY
Harry J. Jones - Austin TX
Shashi D. Malaviya - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19013, H03K 19086, H03K 1704, H03K 1760
US Classification:
307455
Abstract:
A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors, the collector dotting of their respective reference transistors, the emitter dotting of one input transistor and a reference transistor to a constant current source, the emitter dotting of the other input transistor and the other reference transistor to a different constant current source, and an inhibit circuit for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.