MR. HARRY GARDNER, LPC
Social Work at Colorado Ave, Colorado Springs, CO

4275380, Jun 23, 1981

May 30, 1979

6/043930

Harry N. Gardner - Colorado Springs CO
Wayne R. Gravelle - Colorado Springs CO

NCR Corporation - Dayton OH

G06K 714

3401463Z

An integrated circuit for sequentially receiving a plurality of digital character words produced in response to optical scanning of a bar coded label and a plurality of corresponding binary signals representing, respectively, validity, scanning direction, and timing of the digital character words includes first, second, third, and fourth sequentially located edges forming a rectangle. The integrated circuit includes input circuitry for receiving the digital character words and corresponding binary signals and further includes twelve shift registers for storing predetermined ones of the digital character words. Four frame counters and associated control circuitry responsive to the binary signals and the character words steer the incoming character words to predetermined ones of the shift registers. The integrated circuit outputs formatted character words to a digital processor system. A command decoder receiving commands from a digital processor system controls the outputting of valid, properly formatted digital character words from predetermined ones of the shift registers in response to an interrupt signal produced when a properly formatted character word is contained in one of the shift registers.

6831496, Dec 14, 2004

Nov 19, 2002

10/299461

Harry N. Gardner - Colorado Springs CO

Aeroflex UTMC Microelectronic Systems, Inc. - Colorado Springs CO

H03K 3289

327202, 714797

An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

6453447, Sep 17, 2002

Aug 16, 2000

09/640344

Harry N. Gardner - Colorado Springs CO
Debra S. Harris - Colorado Springs CO
Michael D. Lahey - Colorado Springs CO
Stacia L. Patton - Colorado Springs CO
Peter M. Pohlenz - Colorado Springs CO

Aeroflex UTMC Microelectronic Systems Inc. - Colorado Springs CO

G06F 1750

716 3, 715 2, 715 17

Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.

6573774, Jun 3, 2003

Mar 25, 2002

10/107293

Harry N. Gardner - Colorado Springs CO

Aeroflex UTMC Microelectronic Systems, Inc. - Colorado Springs CO

H03K 3037

327201, 327225

An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

6570234, May 27, 2003

Nov 17, 2000

09/715819

Harry Gardner - Colorado Springs CO

Aeroflex UTMC Microelectronic Systems, Inc. - Colorado Springs CO

H01L 2976

257390, 438128, 438279

Annular transistors are positioned with respect to the n-well diffusion region so that the active channels of the transistors are completely within the diffusion region, thereby avoiding the formation of the edges at the boundary between n active channel regions and adjacent field oxide region (the birds beak region), which are susceptible to the effect of the ionizing radiation. The edgeless design of the gate arrays reduces the degradation of the transistors caused by the birds beak leakage, while allowing for an unmodified commercial process flow for fabrication. An outer annular transistor and one or more inner annular transistors may be provided. The outer transistor may be used as an active transistor in the formation of logic circuits, or may provide isolation for the one or more inner transistors, which may be connected to form logic circuits. The design preferably includes a provision for readily disabling the radiation resistant system so the same design can be easily transformed into a non-radiation resistant design. Other electrical components such as a resistor may be formed with another annular gate electrode to isolate the component from the deleterious effects of ionizing radiation, as well.

5870332, Feb 9, 1999

Apr 22, 1996

8/635794

Michael D. Lahey - Colorado Springs CO
Debra S. Harris - Colorado Springs CO
Harry N. Gardner - Colorado Springs CO
Michael J. Barry - Tigard OR

United Technologies Corporation - Hartford CT

G11C 1140

365156

A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states. The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell. The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.

7737535, Jun 15, 2010

Mar 16, 2007

11/687588

Harry N. Gardner - Colorado Springs CO, US

Aeroflex Colorado Springs Inc. - Colorado Springs CO

H01L 23/552

257659, 257921, 257E23114, 438953

A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

2012027, Nov 1, 2012

Jul 13, 2012

13/549225

Radu Dumitru - Colorado Springs CO, US
Harry Gardner - Colorado Springs CO, US

Aeroflex Colorado Springs Inc. - Colorado Springs CO

H03K 19/00

326 16

A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

5543736, Aug 6, 1996

Dec 10, 1993

8/165236

Harry N. Gardner - Colorado Springs CO
Charles R. Gregory - Colorado Springs CO
Douglas W. Garvie - Colorado Springs CO

United Technologies Corporation - Hartford CT

H01L 2500, H03K 1900

326101

The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.

8222916, Jul 17, 2012

Nov 17, 2010

12/948004

Radu Dumitru - Colorado Springs CO, US
Harry Gardner - Colorado Springs CO, US

Aeroflex Colorado Springs Inc. - Colorado Springs CO

H03K 19/00

326 16

A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.