Location:
Sacramento, California Area
Work:
Intel
since Oct 2008
-
Design Engineer
IET, Bhaddal
Feb 2006 - Jul 2006
-
Lecturer
Central Scientific Instruments Organization
Aug 2004 - Jan 2005
-
Intern
Education:
University of Southern California 2006 - 2008
MS, Electrical Engineering
Punjab Technical University 2001 - 2005
B.Tech., Electronics & Instrumentation
Skills:
VLSI, ModelSim, Verilog, VHDL, Scripting, Performance Verification, Static Timing Analysis, EDA
Honor & Awards:
- Intel DTTC 2011 Paper
Multicore Resource Management Flow - Approach to overcome GT high capacity PV
- Division Recognition Award 2010
For enabling partition level PV under Synthesis environment.