HAROLD D KOSSMAN, LICSW
Social Work at 1 St, Rochester, MN

7096470, Aug 22, 2006

Sep 19, 2002

10/246912

Jeffrey Douglas Brown - Rochester MN, US
Harold F. Kossman - Rochester MN, US
Timothy John Mullins - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 9/46, G06F 15/00

718102, 712 1, 712216, 712228, 712233

A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. Each stored thread state includes predefined selection data. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, uses the stored predefined selection data for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.

6965986, Nov 15, 2005

Sep 19, 2002

10/246937

Harold F. Kossman - Rochester MN, US
Timothy John Mullins - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F009/48

712228

A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.

2008020, Aug 21, 2008

Apr 24, 2008

12/109011

Jeffrey Powers Bradford - Rochester MN, US
Harold F. Kossman - Rochester MN, US
Timothy John Mullins - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 9/30

712239, 712E09016

An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

7383391, Jun 3, 2008

May 18, 2005

11/131582

Gordon Taylor Davis - Chapel Hill NC, US
Thomas B. Genduso - Apex NC, US
Harold F. Kossman - Rochester MN, US
Robert W. Todd - Raleigh NC, US

International Business Machines Corporation - Armonk NY

G06F 9/34, G06F 12/10

711137, 711206

A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

2008020, Aug 21, 2008

Apr 24, 2008

12/108998

Jeffrey Powers Bradford - Rochester MN, US
Harold F. Kossman - Rochester MN, US
Timothy John Mullins - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 9/32, G06F 12/08

711125, 712207, 711E12016, 712E09073

An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

2008015, Jun 26, 2008

Mar 11, 2008

12/046345

Gordon Taylor DAVIS - Chapel Hill NC, US
Thomas B. Genduso - Apex NC, US
Harold F. Kossman - Rochester MN, US
Robert W. Todd - Raleigh NC, US

International Business Machines Corporation - Armonk NY

G06F 12/10, G06F 12/00

711207, 711213, 711E12059, 711E12061

A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

2007008, Apr 12, 2007

Oct 7, 2005

11/246819

Jeffrey Bradford - Rochester MN, US
Todd Christensen - Rochester MN, US
Richard Eickemeyer - Rochester MN, US
Timothy Heil - Rochester MN, US
Harold Kossman - Rochester MN, US
Timothy Mullins - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711118000

A method, apparatus and computer program product are provided for implementing polymorphic reconfiguration of a cache size. A cache includes a plurality of physical sub-banks. A first cache configuration is provided. Then checking is provided to identify improved performance with another cache configuration. The cache size is reconfigured to provide improved performance based upon the current workload.

2007008, Apr 12, 2007

Oct 7, 2005

11/246818

Jeffrey Bradford - Rochester MN, US
Richard Eickemeyer - Rochester MN, US
Timothy Heil - Rochester MN, US
Harold Kossman - Rochester MN, US
Timothy Mullins - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711118000

In a method of using a cache in a computer, the computer is monitored to detect an event that indicates that the cache is to be reconfigured into a metadata state. When the event is detected, the cache is reconfigured so that a predetermined portion of the cache stores metadata. A computational circuit employed in association with a computer includes a cache, a cache event detector circuit, and a cache reconfiguration circuit. The cache event detector circuit detects an event relative to the cache. The cache reconfiguration circuit reconfigures the cache so that a predetermined portion of the cache stores metadata when the cache event detector circuit detects the event.

6061710, May 9, 2000

Oct 29, 1997

8/960744

Richard James Eickemeyer - Rochester MN
Harold F. Kossman - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 946

709107

A method of using multithreading resources for improving handling instructions is operated by an improved multithreaded processor which includes a context select logic unit being arranged and configured for receiving and responding an interrupt including: a first controller for setting a pending thread latch when a hardware context is not available for executing a new thread for servicing the interrupt.