HAO TH NGUYEN, M.D.
Medical Practice at Samaritan Dr, San Jose, CA

2013017, Jul 11, 2013

Aug 9, 2012

13/570746

Hao Thai Nguyen - San Jose CA, US
Juan Carlos Lee - Sunnyvale CA, US
Seungpil Lee - San Ramon CA, US
Masahide Matsumoto - Setagaya, JP
Jongmin Park - Cupertino CA, US
Man Lung Mui - Fremont CA, US
Sung-En Wang - San Jose CA, US

G11C 16/12, G11C 16/04

36518503

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

2013017, Jul 11, 2013

Aug 9, 2012

13/570779

Hao Thai Nguyen - San Jose CA, US
Juan Carlos Lee - Sunnyvale CA, US
Seungpil Lee - San Ramon CA, US
Jongmin Park - Cupertino CA, US
Man Lung Mui - Fremont CA, US

G11C 16/12, G11C 16/04

36518503

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

7532516, May 12, 2009

Jun 29, 2007

11/771987

Hao Thai Nguyen - San Jose CA, US
Seungpil Lee - San Ramon CA, US
Man Lung Mui - Santa Clara CA, US
Shahzad Khalid - Union City CA, US
Hock So - Redwood City CA, US
Prashanti Govindu - Santa Clara CA, US
Nima Mokhlesi - Los Gatos CA, US
Deepak Chandra Sekar - Atlanta GA, US

SanDisk Corporation - Milpitas CA

G11C 16/04, G11C 16/06

36518521, 36518517, 36518518

A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

8300472, Oct 30, 2012

Jul 8, 2011

13/178690

Hao Thai Nguyen - San Jose CA, US
Man Lung Mui - Fremont CA, US
Seungpil Lee - San Ramon CA, US

SanDisk Technologies Inc. - Plano TX

G11C 16/26

36518521, 36518522, 36518525, 36518512, 36518511, 36518517, 36518502, 36518533

In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

7539060, May 26, 2009

Jun 29, 2007

11/771997

Hao Thai Nguyen - San Jose CA, US
Seungpil Lee - San Ramon CA, US
Man Lung Mui - Santa Clara CA, US
Shahzad Khalid - Union City CA, US
Hock So - Redwood City CA, US
Prashanti Govindu - Santa Clara CA, US

SanDisk Corporation - Milpitas CA

G11C 16/04, G11C 16/06

36518521, 36518517, 36518527

A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

2008024, Oct 9, 2008

Jun 29, 2007

11/772015

Hao Thai Nguyen - San Jose CA, US
Seungpil Lee - San Ramon CA, US
Man Lung Mui - Santa Clara CA, US

G11C 7/04

365212

Temperature-compensation is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated.

7545678, Jun 9, 2009

Jun 29, 2007

11/772009

Seungpil Lee - San Ramon CA, US
Hao Thai Nguyen - San Jose CA, US
Man Lung Mui - Santa Clara CA, US

SanDisk Corporation - Milpitas CA

G11C 16/06, G11C 16/04

36518521, 36518517, 36518518

A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

2014003, Feb 6, 2014

Oct 7, 2013

14/048015

Yingda Dong - San Jose CA, US
Gerrit Jan Hemink - Yokohama, JP
Man Lung Mui - Santa Clara CA, US
Hao Nguyen - San Jose CA, US
Seungpil Lee - San Ramon CA, US
Jong Park - Campbell CA, US
Fanglin Zhang - Fremont CA, US

SANDISK TECHNOLOGIES INC. - Plano TX

G11C 16/34

36518522

A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.