DR. GREGORY G JOHNSON, M.D.
Osteopathic Medicine at Colby Ave, Everett, WA

License number
Washington MD00046216
Category
Osteopathic Medicine
Type
Emergency Medicine
Address
Address 2
1321 Colby Ave, Everett, WA 98201
494 E Historic St, Tucson, AZ 85701
Phone
(425) 261-2000
(253) 449-5307

Personal information

See more information about GREGORY G JOHNSON at radaris.com
Name
Address
Phone
Gregory Johnson, age 55
5006 Deception Cir, Oak Harbor, WA 98277
(360) 675-6252
Gregory Johnson
4952 E Harmony Ave, Mesa, AZ 85206
(480) 225-7826
Gregory Johnson, age 73
4917 S 164Th St, Tukwila, WA 98188
(206) 244-2560
Gregory Johnson, age 58
513 Pine Ave, Snohomish, WA 98290

Professional information

See more information about GREGORY G JOHNSON at trustoria.com
Gregory Johnson Photo 1
Design Engineer At Texas Insruments

Design Engineer At Texas Insruments

Position:
Design Engineer at Texas Insruments
Location:
Tucson, Arizona Area
Industry:
Electrical/Electronic Manufacturing
Work:
Texas Insruments - Design Engineer
Education:
University of Arizona 1983 - 1992


Gregory G Johnson Photo 2
Dr. Gregory G Johnson, Everett WA - MD (Doctor of Medicine)

Dr. Gregory G Johnson, Everett WA - MD (Doctor of Medicine)

Specialties:
Emergency Medicine
Address:
1716 W Marine View Dr SUITE C, Everett 98201
(425) 259-0212 (Phone)
1321 Colby Ave, Everett 98201
(425) 261-2000 (Phone), (405) 682-1586 (Fax)
Certifications:
Emergency Medicine, 2007
Awards:
Healthgrades Honor Roll
Languages:
English
Hospitals:
1716 W Marine View Dr SUITE C, Everett 98201
1321 Colby Ave, Everett 98201
Providence Regional Medical Center Everett
1321 Colby Ave, Everett 98201
Education:
Medical School
Baylor University
Graduated: 1978
University of Washington
Graduated: 2002
University Of Arizona
Graduated: 2006


Gregory Johnson Photo 3
Slew Rate Boost Circuitry And Method

Slew Rate Boost Circuitry And Method

US Patent:
6359512, Mar 19, 2002
Filed:
Jan 18, 2001
Appl. No.:
09/765267
Inventors:
Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ
Gregory H. Johnson - Tucson AZ
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 345
US Classification:
330255, 330264, 330267
Abstract:
An operational amplifier includes a differential input stage ( ) having first ( ) and second ( ) input conductors, a class AB output stage ( ) coupled to an output of the differential input stage ( ) and including a pull-up transistor (M ) having a source coupled to a first supply voltage (V ), a drain coupled to an output conductor ( ), and a gate coupled to a first terminal ( ) of a class AB control circuit ( ), and a pull-down transistor (M ) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor ( ), and a gate coupled to a second terminal ( ) of the class AB control circuit ( ). A differential input signal is applied between the first ( ) and second ( ) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier ( ) and between first and second input to the second unbalanced differential amplifier ( ). If the differential input signal is of a first polarity and is of a magnitude substantially greater than a threshold voltage of the first unbalanced differential amplifier ( ), the magnitude of a turn-on voltage of the pull-down transistor (M ) is decreased and the magnitude of a turn-on voltage of the pull-up transistor (M ) is increased in response to an output voltage produced by the first unbalanced differential amplifier ( ). However, if the differential input signal is of a second polarity and is of a magnitude substantially greater than a threshold voltage of the second unbalanced differential amplifier ( ), then the magnitude of a turn-on voltage of the pull-up transistor (M ) is increased and the magnitude of a turn-on voltage of the pull-down transistor (M ) is simultaneously decreased, in response to an output voltage produced by the second unbalanced differential amplifier ( ).


Gregory Johnson Photo 4
Rail-To-Rail Class Ab Output Stage For Operational Amplifier With Wide Supply Range

Rail-To-Rail Class Ab Output Stage For Operational Amplifier With Wide Supply Range

US Patent:
6545538, Apr 8, 2003
Filed:
Oct 3, 2000
Appl. No.:
09/677967
Inventors:
Vadim V. Ivanov - Tucson AZ
Gregory H. Johnson - Tuscon AZ
Stephen J. Sanchez - Tucson AZ
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 345
US Classification:
330255, 330253, 330261
Abstract:
A rail-to-rail class AB output stage includes a P-channel pull-up transistor ( ) having a source coupled to a first supply rail voltage (V ), a gate coupled to a first input conductor ( ) of the output stage, and a drain coupled to an output terminal ( ) of the output stage. An N-channel pull-down transistor ( ) includes a source coupled to a second supply rail voltage (GROUND), a gate coupled to a second input conductor ( ) of the output stage, and a drain coupled to the output terminal ( ). A P-channel first bias transistor ( ) includes a source coupled to the first input conductor ( ) and a drain coupled to the second input terminal ( ). A first bias circuit coupled between the first and second supply rail voltages produces a first bias voltage ( ) on a gate of the first bias transistor ( ). A P-channel second bias transistor ( ) includes a source coupled to be first input conductor ( ). An N-channel third bias transistor ( ) includes a source coupled to the second input terminal ( ) and a drain connected to a drain of the second bias transistor ( ) and to a non-inverting input of a servo amplifier ( ) having an output coupled to a gate of the second bias transistor ( ) and an inverting input coupled to a gate of the third bias transistor ( ) or a suitable reference voltage.


Gregory Johnson Photo 5
Rail-To-Rail Input/Output Operational Amplifier And Method

Rail-To-Rail Input/Output Operational Amplifier And Method

US Patent:
6356153, Mar 12, 2002
Filed:
Nov 20, 2000
Appl. No.:
09/717186
Inventors:
Vadim V. Ivanov - Tucson AZ
Gregory H. Johnson - Tucson AZ
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 345
US Classification:
330253, 330255
Abstract:
A rail-to-rail differential amplifier includes first and second input terminals, and an output terminal and an input stage including differentially connected N-channel first and second input transistors, and differentially connected P-channel third and fourth input transistors. A P-channel first cascode transistor has a source coupled to a first supply voltage to the drain of the first input transistor. An N-channel cascode transistor has a source coupled by a second resistive element to a second supply voltage and to the drain of the third input transistor. A first gain boost amplifier has an output coupled to a gate of the first cascode transistor, a first input coupled to the source of the first cascode transistor and the drain of the first input transistor, and a second input coupled to a drain of the second input transistor and a bias control circuit. A second gain boost amplifier has an output coupled to a gate of the second cascode transistor, a first input coupled to the source of the second cascode transistor and to the drain of the third input transistor, and a second input coupled to a drain of the fourth input transistor and the bias control circuit. An output stage includes a pull-up transistor coupled between the first supply voltage and the output terminal, a pull-down transistor coupled between the second supply voltage and the output terminal, and a class AB bias circuit coupled between drain electrodes of the fist and second cascode transistors and between gate electrodes of the pull-up and pull-down transistors.


Gregory Johnson Photo 6
Fast, Stable Overload Recovery Circuit And Method

Fast, Stable Overload Recovery Circuit And Method

US Patent:
6703900, Mar 9, 2004
Filed:
Jun 5, 2002
Appl. No.:
10/163113
Inventors:
Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ
Gregory H. Johnson - Tucson AZ
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 152
US Classification:
330255, 330264, 330267
Abstract:
A differential amplifier includes an input stage ( ) and an output stage ( ) including an output transistor (M ) having a source coupled to a supply voltage (V ), a gate coupled to a terminal ( ) of the input stage, and a drain coupled to an output conductor ( ). A recovery circuit ( A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M ) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier ( A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.


Gregory Johnson Photo 7
Overload Recovery Circuit And Method

Overload Recovery Circuit And Method

US Patent:
6317000, Nov 13, 2001
Filed:
Jan 18, 2001
Appl. No.:
9/765485
Inventors:
Vadim V. Ivanov - Tucson AZ
Shilong Zhang - Tucson AZ
Gregory H. Johnson - Tucson AZ
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 345
US Classification:
330255
Abstract:
An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (V. sub. DD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (V. sub. SS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor. A first overload recovery circuit (X) is coupled between the output conductor (22) and the gate of the pull-up transistor for limiting the voltage on the gate of the pull-up transistor in response to the output voltage (Vout) when the output voltage is within a first predetermined range of the first supply voltage (V. sub. DD). A second overload recovery circuit (Y) is coupled between the output conductor (22) and the gate of the pull-down transistor for limiting the voltage on the gate of the pull-down transistor in response to the output voltage (Vout) when the output voltage is within a second predetermined range of the second supply voltage (V. sub. SS).