Gregory Don Smith
Plumbers at Kinnikinnik Dr, Colorado Springs, CO

5479132, Dec 26, 1995

Jun 6, 1994

8/254281

Donald J. Verhaeghe - Colorado Springs CO
Gregory M. Smith - Colorado Springs CO

Ramtron International Corporation - Colorado Springs CO

H03K 500

327553

A filter circuit includes an input node for receiving an unfiltered input signal, an output node for providing a filtered output signal, and an intermediate node. An integrator has an input coupled to the input node and an output coupled to the intermediate node. A Schmitt trigger has an input coupled to the intermediate node and an output coupled to the output node. A reset circuit has a first input coupled to the input node, a second input coupled to the output node, and an output coupled to the intermediate node. The signal on the intermediate node is generated by integrating the unfiltered logic input signal if the input signal and the output signal are at opposite logic states. A filtered output logic signal is generated by conditioning the intermediate signal with the Schmitt trigger. The reset circuit resets the intermediate signal if the input signal and the output signal are each at a zero logic state or if the input signal and the output signal are each at a one logic state.

5533061, Jul 2, 1996

Feb 10, 1994

8/194694

Gregory M. Smith - Colorado Springs CO
Michael W. Yeager - Colorado Springs CO
J. Donald Pauley - Estes Park CO
Gary T. Carroll - Boulder CO

Racom Systems, Inc. - Englewood CO

H03D 300

375334

An integrated FSK detector circuit includes a first counter that receives a carrier signal and provides a multiple-bit output for reducing the frequency of the carrier signal into a plurality of weighted sub-multiples. An oscillator enable decoder circuit provides predetermined calibrate and measure pulses in response to the first counter output. A gated oscillator receives the calibrate and measure pulses and provides a burst of oscillator pulses during these time intervals. A second counter has an input coupled to the output of the gated oscillator and an up/down control terminal coupled to the output of the first counter. The output of the second counter also provides a multiple-bit output for reducing the frequency of the gated oscillator pulses. An FSK decoder logic circuit decodes the multiple-bit output of the second counter into a single bit FSK detect signal. The FSK detector circuit also includes a reset circuit coupled to the first counter for resetting between FSK detections.

5479172, Dec 26, 1995

Feb 10, 1994

8/194707

Gregory M. Smith - Colorado Springs CO
Michael W. Yeager - Colorado Springs CO
J. Donald Pauley - Estes Park CO
Gary T. Carroll - Boulder CO

Racom Systems, Inc. - Englewood CO

G01S 1375

342 51

A power supply self-contained within a portable RF/ID transponder includes a full wave rectifier having an input for receiving an antenna signal and outputs for providing power supply and ground voltages, wherein the power supply voltage has a time varying voltage waveform corresponding to the electric field generated by a reader/controller. The power supply further includes a clamping circuit for regulating the power supply voltage and a ferroelectric filter/storage capacitor coupled between the power supply and ground outputs of the full wave rectifier. The power supply further includes a power enable circuit for constantly monitoring the supply voltage waveform and for providing a power enable indication after an initial portion of the supply voltage waveform rises above a predetermined power-up threshold level and for removing the power enable indication when a terminal portion of the supply voltage waveform falls below a predetermined power-down level. The power-up and power-down thresholds describe a proper voltage range of operation for the ferroelectric memory in the transponder. The power enable indication is provided to the ferroelectric memory so that the memory is only operated when the power supply voltage is within the proper range so that data is valid during read and write operations.