DR. GREGORY CHARLES TAYLOR, M.D
Anesthesiologist Assistant at Barnes Rd, Portland, OR

6691241, Feb 10, 2004

Dec 21, 1999

09/469848

Gregory F. Taylor - Portland OR

Intel Corporation - Santa Clara CA

G06F 104

713500, 713400

A shared bus multiprocessor system is provided. The system comprises a communications bus, a first processor, a second processor, and a clock. The first processor has a first output buffer that has a first output delay time. The second processor has a second output buffer that has a second output delay time. The second output delay time is less than the first output delay time. Finally, the clock provides a clock signal to the first and second processors, with the clock signal arriving at the second processor before the first processor.

6535047, Mar 18, 2003

May 17, 2001

09/861155

Usman A. Mughal - Hillsboro OR
Razi Uddin - Orangevale CA
Chee How Lim - Hillsboro OR
Songmin Kim - Beaverton OR
Gregory F. Taylor - Portland OR

Intel Corporation - Santa Clara CA

H03K 1714

327378, 327170, 326 30, 326 86

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is provided (as a slave impedance code) to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e. g. , shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation. Using the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs.

5306964, Apr 26, 1994

Feb 22, 1993

8/020651

Gregory F. Taylor - Portland OR

Intel Corporation - Santa Clara CA

H03K 1902, H03K 19086

307446

A reference circuit for coupling to a particular type of BiCMOS logic gate includes a V. sub. be multiplier coupled between V. sub. CC and a first internal node. The multiplier establishes a predetermined potential at the internal node which determines the voltage swing across the PMOS load devices utilized in the BiCMOS logic gate. A first PMOS transistor, configured as a current source within the multiplier, has its source coupled to the internal node. A second PMOS transistor has its gate coupled to the gate and drain of the first PMOS transistor in a source-follower configuration so as to drive the source node of the second PMOS transistor to the predetermined potential. A reference PMOS transistor is coupled between V. sub. CC and the source node of the second PMOS transistor, with the gate of the reference PMOS transistor being commonly coupled to the gates of the PMOS load devices and to a reference potential. A NMOS current source device is coupled to the source of the second PMOS transistor such that a reference current flows through the reference PMOS transistor; this current is then mirrored through the PMOS load devices of the BiCMOS logic gate.

6075285, Jun 13, 2000

Dec 15, 1997

8/990705

Gregory F. Taylor - Portland OR
George L. Geannopoulos - Portland OR
Larry E. Mosley - Sunnyvale CA

Intel Corporation - Santa Clara CA

H01L 2352

257691

An apparatus that efficiently delivers electrical power and lowers the inductance to an integrated circuit. In one embodiment, the present invention includes an apparatus for delivering electrical power to an integrated circuit comprising two planes, substantially parallel to one another, having many ground and power traces. The ground and power traces of the separate planes are connected together and connected to the integrated circuit, thereby providing power to the integrated circuit. In each individual plane, the ground and power traces are substantially parallel to each other, one array of traces in one plane substantially perpendicular to another array of traces in another plane. The apparatus being electrically coupled to a printed circuit board having at least one decoupling capacitor with first and second electrodes coupled to at least two of the ground and power connections, respectively, of the integrated circuit through the printed circuit board, and the first and second ground and power planes.

6874083, Mar 29, 2005

Dec 22, 2000

09/746168

Ananda Sarangi - Beaverton OR, US
Rachael Jade Parker - Forest Grove OR, US
Edward P. Osburn - Folsom CA, US
Gregory F. Taylor - Portland OR, US

Intel Corporation - Santa Clara CA

G06F001/24, G06F001/32

713100, 713 1, 713 2, 713300, 713320, 713322

A dynamic processor configuration and power-up programs a processor's fuse block with configuration signals during processor manufacturing. The processor configuration signals include a core voltage identifier and a system bus frequency identifier. When power is applied to the platform, a control signal is used to prevent power-up of the platform's processor related circuitry. While the platform awaits full power-up, the fuse block is powered up. When the fuse block is powered up, the control signal is used to allow the configuration signals to be read from the fuse block. The processor is configured with core voltage and system bus frequency based on the values read from the fuse block. The platform then performs its boot-up sequence.

8314725, Nov 20, 2012

Sep 15, 2010

12/883125

Paola Zepeda - Chandler AZ, US
David E. Duarte - Portland OR, US
Gregory F. Taylor - Portland OR, US
Atul Maheshwari - Portland OR, US

Intel Corporation - Santa Clara CA

H03M 1/10

341120, 341118, 341119, 341121, 341155

In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.

6208169, Mar 27, 2001

Jun 28, 1999

9/340975

Keng L. Wong - Portland OR
Gregory F. Taylor - Portland OR
Ravishankar Kuppuswamy - Hillsboro OR
Douglas R. Parker - Forest Grove OR
Kent R. Callahan - Hillsboro OR
Xia Dai - Chavez Way CA

Intel Corporation - Santa Clara CA

H03K19/096

326 93

An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.

7602663, Oct 13, 2009

Dec 22, 2006

11/644381

Zhanping Chen - Portland OR, US
Jonathan P. Douglas - Portland OR, US
Praveen Mosalikanti - Portland OR, US
Kevin Zhang - Portland OR, US
Gregory F. Taylor - Portland OR, US

Intel Corporation - Santa Clara CA

G11C 17/18

3652257, 36518906, 36518907

A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

7199624, Apr 3, 2007

Apr 30, 2003

10/425914

Keng L. Wong - Portland OR, US
Gregory F. Taylor - Portland OR, US
Chee How Lim - Beaverton OR, US

Intel Corporation - Santa Clara CA

H03L 7/06

327149, 327158

A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.