Greg Allen
Architects in Boise, ID

2007008, Apr 19, 2007

Oct 19, 2005

11/253317

Thomas Wheless - Eagle ID, US
Greg Allen - Boise ID, US
Randall Briggs - Boise ID, US
Mark Montierth - Meridian ID, US
Michael Cusack - Boise ID, US

G06F 3/12

358001130

A printer device includes a printer engine controller in communication with a print mechanism and a printer formatter. The printer formatter includes a quad flat pack (QFP) package having an application specific integrated circuit (ASIC) mounted and a memory device mounted therein. The printer device further includes a substrate having the QFP package and the printer engine controller mounted thereon.

6659512, Dec 9, 2003

Jul 18, 2002

10/199441

Timothy V. Harper - Boise ID
Greg L. Allen - Boise ID

Hewlett-Packard Development Company, L.P. - Houston TX

H01L 2940

287777, 257786

An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

2004003, Feb 26, 2004

Sep 30, 2003

10/677078

Timothy Harper - Boise ID, US
Greg Allen - Boise ID, US

H01L023/495

257/666000

An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

7002254, Feb 21, 2006

Aug 6, 2003

10/636993

Timothy V. Harper - Boise ID, US
Greg L. Allen - Boise ID, US

Hewlett-Packard Development Company, L.P. - Houston TX

H01L 23/48

257777, 257723, 257786

An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

5444827, Aug 22, 1995

May 23, 1994

8/247806

Randall D. Briggs - Boise ID
Greg L. Allen - Boise ID

Hewlett-Packard Company - Palo Alto CA

G06K 1500

395115

A page printer includes a variable frequency clock for producing at least two clock frequencies, one higher than the other. The page printer includes a first memory for storing a page processing procedure and a second memory for storing data comprising full page strips. A processor operates at the first clock frequency in conjunction with the page processing procedure and derives a rasterization execution time (RET) for display commands that define images to be printed in each page strip of a page. The processor compares the RET for each page strip with a threshold value and rasterizes in the standard manner any page strip whose RET is equal to or less than the threshold value (while operating under the influence of the first clock frequency). When a complex page strip is found (whose RET exceeds the threshold), the variable frequency clock is controlled to generate a second higher frequency clock signal and to cause the processor to operate at a rate determined by the higher clock frequency so that display commands in the complex page strip are rasterized at higher speed.

5253357, Oct 12, 1993

Jun 13, 1991

7/715077

Greg L. Allen - Boise ID
Lynn R. Watson - Boise ID

Hewlett-Packard Company - Palo Alto CA

G06F 1206

395425

A system is described that includes an arithmetic logic unit that senses the presence of a circuit module in a connector, wherein one type of circuit module, if present, automatically provides a set of signals on a predetermined pin set that indicates characteristics of the circuit module. The system also includes circuitry that enables the determination of the presence of other types of pluggable circuit modules in the connector. The circuitry comprises a latch circuit for holding a received address for the circuit module. In the received address, a preset field of bits is present which identifies a field in a status register. The status register stores n fields of information defining the characteristics of the pluggable circuit module and is responsive to the preset field of bits to provide signals on the predetermined pin set indicating the information.

2004001, Jan 22, 2004

Jul 18, 2002

10/199438

Timothy Harper - Boise ID, US
Greg Allen - Boise ID, US

H01L023/34

257/777000, 257/723000

An integrated circuit package includes a package substrate having a first surface including an array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including a first array of interconnection sites, and a second array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the package substrate. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

2003013, Jul 10, 2003

Jan 9, 2002

10/044080

Richard Taylor - Eagle ID, US
Greg Allen - Boise ID, US

H04L001/22

714/005000

A method and apparatus for protecting cache memories from soft errors. Entries in the cache's data store and tag memory are associated with parity bits. During a read cycle, the parity bits are checked and data retrieved only if the parity checks indicate no errors.

2006026, Nov 30, 2006

May 27, 2005

11/139248

Greg Allen - Boise ID, US
Randall Briggs - Boise ID, US

H01L 23/48

257786000

An integrated-circuit die includes a number of signal paths, and includes a greater number of signal pads that are operable to be coupled to the signal paths. By including more signal pads than signal paths on the die, one can often repair a defect in the connection of a pad to, e.g., a pad of another die, by connecting a signal path to another, i.e., redundant, pad. And such repairing of a pad-connection defect can often increase the yield of the integrated circuits incorporating such a die and/or can extend the lifetime of such an integrated circuit.