GLEN EDWARD OFFORD
Engineers in Macungie, PA

5901075, May 4, 1999

Dec 22, 1995

8/577890

Glen Edward Offord - Macungie PA
Jeffrey Lee Sonntag - Rockland Township PA

Lucent Technologies Inc. - Murray Hill NJ

G06F 1710

36472419

An apparatus and a scheme for adapting a plurality of tap weights in an FIR filter wherein tap weights are adapted for a current data cycle utilizing a current subset of data and the tap weights are adapted for a next data cycle utilizing a next subset of data is described. A method of adapting the plurality of tap weights in an adaptive FIR filter comprises assigning a current time slot for a timeshared tap weight processor during a current data cycle and assigning a different time slot for the timeshared tap weight processor during a next data cycle. The tap weights are adapted for the current data cycle utilizing a current subset of data and the tap weights are adapted for the next data cycle utilizing a next subset of data. In a further enhancement of the present invention method the different time slot for the next data cycle is assigned by rotating time slot assignments for the timeshared tap weight processor. An apparatus for adapting the plurality of tap weights comprises a circuit assigning a current time slot for the timeshared tap weight processor during a current data cycle and assigning a different time slot for the timeshared tap weight processor during a next data cycle.

2007012, May 31, 2007

Nov 30, 2005

11/289892

Glen Offord - Macungie PA, US
Phillip Johnson - Hellertown PA, US

H04L 5/16

375219000

In one embodiment of the invention, a phase-locked loop (PLL) can be programmably controlled to add jitter to its PLL output clock. Such a PLL can be used to programmably inject jitter into the outgoing serial data signal generated by a serializer/de-serializer (serdes) that can be operated in an internal loopback mode, in which the outgoing serial data signal is internally looped back from the transmitter side of the serdes to the serdes receiver side. Jitter logic associated with the PLL can be operated in a register-based mode that does not rely on any externally generated jitter clock. Such register-based processing enables effective (1) internal loopback testing of unpackaged devices at the wafer stage as well as package devices at the package stage and (2) external loopback testing at the system level.

5522048, May 28, 1996

Nov 30, 1993

8/159178

Glen E. Offord - Macungie PA

AT&T Corp. - Murray Hill NJ

H04L 700

395280

An asynchronous to synchronous interface between a master chip and a target chip, the interface being located on the target chip, includes a synchronous write logic unit and one set of synchronous transfer latches. A system clock (clock on target chip) and asynchronous clock signal are connected to the synchronous write logic unit. The asynchronous clock signal is also connected to a set of asynchronous latches, which receive data from the master chip upon receiving active asynchronous clock signals. The asynchronous latches are connected to a set of synchronous latches. The synchronous latches are controlled by a synchronous write signal generated by the synchronous write logic unit. Based on the asynchronous write signal and clock signal of the target chip the synchronous write logic unit synchronously transfers data from the outputs of the asynchronous latches to the outputs of the synchronous latches.

6198323, Mar 6, 2001

Jan 28, 1999

9/238793

Glen E. Offord - Macungie PA

Lucent Technologies Inc. - Murray Hill NJ

H03K 3289

327202

A flip-flop having one or more stages (e. g. , a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage having a driver coupled at its input and output to a feedback path with a gated inverter having embedded preset and/or clear logic. By embedding the preset/clear logic in the feedback path, the driver can be implemented using a simple inverter. Moreover, the preset and/or clear functionality can be added without adversely affecting either the setup time or the clock-to-Q propagation time of the flip-flop.

5513141, Apr 30, 1996

Feb 3, 1995

8/383161

Glen E. Offord - Macungie PA

AT&T Corp. - Murray Hill NJ

G11C 700

36518905

A novel mad/write control register uses the same bus port for reading and writing, while requiting only one unique control line. The technique may be implemented as a "D" type level sense latch. The write operation is similar to standard latch operation: the transmission gate on the D input is turned on while the feedback transmission gate is off. However, for read operation, both transmission gates are enabled, thereby allowing the register output value to drive the bus. A preset or clear capability may optionally be provided. This approach reduces the size of the register as compared to standard read/write registers, and requires only one unique control line versus two, thus reducing decoding logic and routing. Since only one port to the bus is required, the bus load gate capacitance is typically one-half that of the standard approach.

7831754, Nov 9, 2010

Oct 20, 2006

11/551459

Zheng Chen - Allentown PA, US
Glen Edward Offord - Macungie PA, US
Jamie Freed - Fleetwood PA, US

Lattice Semiconductor Corporation - Hillsboro OR

G06F 13/12, G06F 13/38

710 71, 326 38

An integrated circuit includes, in accordance with an embodiment of the present invention, a data port, a system bus for transferring information to and from the data port, and a plurality of SERDES channels. A plurality of registers associated with the plurality of SERDES channels may be written to via the system bus on an individual, group, or global basis to provide communication settings for the SERDES channels.

5550528, Aug 27, 1996

Mar 1, 1995

8/397700

Glen E. Offord - Macungie PA
Jeffrey L. Sonntag - Rockland Township, Berks County PA

Lucent Technologies Inc. - Murray Hill NJ

G05B 100

3401462

A fast, low power and small size approach to matching digital patterns provides for comparing of the input pattern bit-by-bit against the reference pattern to determine matches. In the illustrative embodiment, each mismatch turns on a current source. When the current from mismatches exceeds a maximum current sink value, the pattern mismatch output goes high. Both the reference pattern as well as the number of bits that must match may conveniently be made programmable. This approach is especially useful in "fuzzy" matching, where any N bits of an M bit pattern must match to consider the pattern matched.