GEORGE ALEXANDER VON EDWINS
Pilots at Pepper St, Melbourne, FL

License number
Florida A5306574
Issued Date
Apr 2016
Expiration Date
Apr 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
371 Pepper St NE, Melbourne, FL 32907

Personal information

See more information about GEORGE ALEXANDER VON EDWINS at radaris.com
Name
Address
Phone
George Von, age 71
463 Autumn Ter, Sebastian, FL 32958
(954) 782-8512
George Von, age 90
160 W Trotters Dr, Maitland, FL 32751
(407) 647-5283
George Von, age 70
4828 Ironwood Trl, Bartow, FL 33830
George Von, age 95
10451 Casa Grande Cir, Spring Hill, FL 34608
George Von, age 69
463 Conover Ave NE, Palm Bay, FL 32907
(321) 725-3909

Professional information

See more information about GEORGE ALEXANDER VON EDWINS at trustoria.com
George Von Photo 1
Subsampling Digitizer-Based Frequency Synthesizer

Subsampling Digitizer-Based Frequency Synthesizer

US Patent:
6603362, Aug 5, 2003
Filed:
Mar 14, 2000
Appl. No.:
09/524992
Inventors:
George E. Von Dolteren, Jr. - Palm Bay FL
Assignee:
Intersil Americas Inc. - Irvine CA
International Classification:
H03L 700
US Classification:
331 25, 331 12, 331 16, 375376, 327107, 327159, 327156
Abstract:
A reduced phase noise multiplication, digitally controlled frequency synthesizer employs a subsampling digitizer to downconvert (perform ‘constructive aliasing’ of) the synthesizers output frequency to baseband for precision tuning of the synthesizers output frequency in a digitally controlled phase locked loop. The use of a digitally controlled phase locked loop allows the stepsize of the synthesizer output frequency to be controlled in very small (e. g. , sub-Hertz) increments. Since the phase locked loop uses all digital components for tuning control, no additional frequency division by the loop is required. This means that only the value of the subharmonic ratio ‘n’ of the subsampling clock to the analog-to-digital converter will determine multiplicative phase noise error.


George Von Photo 2
Method And Apparatus For Calibrating Integrated Circuit Analog-To-Digital Converters

Method And Apparatus For Calibrating Integrated Circuit Analog-To-Digital Converters

US Patent:
5861826, Jan 19, 1999
Filed:
Jun 30, 1997
Appl. No.:
8/885273
Inventors:
Tzi-Hsiung Shu - Melbourne FL
George E. Von Dolteren - Palm Bay FL
Assignee:
Harris Corporation - Palm Bay FL
International Classification:
H03M 110
US Classification:
341120
Abstract:
The calibration method preferably comprises the steps of: driving the analog-to-digital converter (ADC) with at least one test signal; calibrating the driven ADC over a series of successive ADC calibrations; generating a series of successive ADC figure of merit measurements for respective successive ADC calibrations, the series of successive ADC figure of merit measurements defining at least a portion of a curve having a local minimum/maximum; and stopping calibrating at an ADC calibration corresponding to the local minimum/maximum of the curve defined by the series of successive ADC figure of merit measurements. The step of calibrating preferably comprises incrementally calibrating the ADC over the series of successive ADC calibrations. The method preferably further comprises the step of determining the local minimum/maximum of the curve. In particular, the step of determining preferably comprises fitting an equation to the series of ADC figure of merit measurements; and calculating the local minimum/maximum based upon the equation.