GARY FRANK DERBENWICK
Pilots at Vickers Dr, Colorado Springs, CO

5843516, Dec 1, 1998

Sep 16, 1996

8/714774

Gary F. Derbenwick - Colorado Springs CO
Larry D. McMillan - Colorado Springs CO
Narayan Solayappan - Colorado Springs CO
Michael C. Scott - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO
Shinichiro Hayashi - Colorado Springs CO

Symetrix Corporation - Colorado Springs CO
Matsushita Electronics Corporation

B05D 512

427 96

A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, a substrate is placed within a vacuum deposition chamber, a small amount of hexamethyl-disilazane is added to the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate. Then an integrated circuit is completed to include at least a portion of the layered superlattice material film in a component of the integrated circuit.

6031754, Feb 29, 2000

Nov 2, 1998

9/184474

Gary F. Derbenwick - Colorado Springs CO
David A. Kamp - Monument CO
Michael Cordoba - Colorado Springs CO
George B. Coombe - Colorado Springs CO

Celis Semiconductor Corporation - Colorado Springs CO

G11C 1122, G11C 700

365145

A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor, and the other electrode of which is connected to a plate line. The bit line is also connected to system ground through a precharge transistor. In a read cycle, the precharge transistor remains on after the word line goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.

7109934, Sep 19, 2006

Jun 29, 2004

10/879379

Alan D. Devilbiss - Colorado Springs CO, US
Gary F. Derbenwick - Colorado Springs CO, US

Celis Semiconductor Corp. - Colorado Springs CO

H01Q 1/22, H01Q 1/38

343720, 343701, 343788, 3405727

A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.

4486943, Dec 11, 1984

Mar 12, 1984

6/588000

William D. Ryden - Colorado Springs CO
Matthew V. Hanson - Colorado Springs CO
Gary F. Derbenwick - Colorado Springs CO
Alfred P. Gnadinger - Colorado Springs CO
James R. Adams - Colorado Springs CO

Inmos Corporation - Colorado Springs CO

H01L 21265

29571

The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

2004024, Dec 9, 2004

Jun 30, 2004

10/880892

Alan Devilbiss - Colorado Springs CO, US
Gary Derbenwick - Colorado Springs CO, US

H02M001/00

307/151000, 340/572700

A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.

6900536, May 31, 2005

Apr 26, 2002

10/132939

Gary F. Derbenwick - Colorado Springs CO, US
Alan D. DeVilbiss - Colorado Springs CO, US

Celis Semiconductor Corporation - Colorado Springs CO

H01L023/34

257724, 257723, 257738, 257737, 257782, 257783

An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.

6178138, Jan 23, 2001

Sep 21, 1999

9/400212

Gary F. Derbenwick - Colorado Springs CO
David A. Kamp - Monument CO
Michael V. Cordoba - Colorado Springs CO
Ryan T. Hirose - Colorado Springs CO

Celis Semiconductor Corporation - Colorado Springs CO

G11C 800

365233

A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.

7053433, May 30, 2006

Apr 29, 2002

10/135488

Gary F. Derbenwick - Colorado Springs CO, US

Celis Semiconductor Corp. - Colorado Springs CO

H01L 27/108

257296, 257297

A ferroelectric layer within an array of ferroelectric FETs is encapsulated between a bottom barrier dielectric layer and a top barrier dielectric layer extending beyond the ferroelectric layer. The ferroelectric FETs are formed on first conductivity type silicon, each having two second conductivity type silicon regions within the first conductivity type silicon separated by some distance. The two second conductivity type silicon regions forming a source and a drain with a channel region therebetween. A silicon dioxide layer is formed on the channel region, a bottom barrier dielectric layer is formed on the silicon dioxide layer, a ferroelectric layer is formed on the bottom barrier dielectric layer, a top barrier dielectric layer is formed on the ferroelectric layer, and an electrode layer is formed on the ferroelectric layer.

6201731, Mar 13, 2001

May 28, 1999

9/322490

David A. Kamp - Monument CO
Gary F. Derbenwick - Colorado Springs CO
George B. Coombe - Colorado Springs CO
Troy A. Meester - Colorado Springs CO

Celis Semiconductor Corporation - Colorado Springs CO

C11C 1604

36518502

A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.

7078304, Jul 18, 2006

Apr 4, 2005

11/098738

Gary F. Derbenwick - Colorado Springs CO, US
Alan D. DeVilbiss - Colorado Springs CO, US

Celis Semiconductor Corporation - Colorado Springs CO

H01L 21/8222

438329, 257528, 257531

An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.