Inventors:
Victor A. Acuña - Rochester MN, US
Dale L. Elson - Round Rock TX, US
Mark J. Hickey - Rochester MN, US
Galen A. Lyle - Fort Collins CO, US
Ibrahim A. Ouda - Rochester MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 12/00
US Classification:
711103, 711167, 711105, 711E12008
Abstract:
A method includes receiving, from a processor, a first read request mapped including a first read request address to a first memory location of a register array and a second read request including a second read request address to a second memory location of a register array. The method includes assigning a first simulated time delay to the first read request and assigning a second simulated time delay to the second read request. The method includes, in response to a first elapsed time being equal to the first simulated time delay, outputting a first read request response including first data. The first elapsed time commences upon receipt of the first read request. The method includes, in response to a second elapsed time being equal to the second simulated time delay, outputting a second read request response including second data. The second elapsed time commences upon receipt of the second read request.