FIRAS N ABUGHAZALEH
Pilots at Lantana Way, Austin, TX

7184511, Feb 27, 2007

Feb 17, 2005

11/059739

Ahmed Younis - Austin TX, US
Firas N. Abughazaleh - Austin TX, US

Xilinx, Inc. - San Jose CA

H03D 3/24, H03L 7/06

375374, 327157

A data density independent clock and data recovery system includes a lock phase adjust charge pump operably coupled to receive phase information and transition information from a phase detector and to produce a current signal, responsive to the phase information and transition information, to a loop filter that converts the current signal to a control voltage signal operably coupled to a voltage controlled oscillator that produces a clock signal to the phase detector based on the control voltage signal. The lock phase adjust charge pump includes a phase charge pump, a transition charge pump, a programmable DC bias current sink, and two programmable offset bias current sinks. The transition charge pump includes a programmable transition current sink. The control logic operates under external control to adjust the currents conducted by the transition charge pump, the programmable DC bias current sink, and the two programmable offset bias current sinks.

7512848, Mar 31, 2009

Sep 29, 2004

10/954391

Firas N. Abughazaleh - Austin TX, US

Xilinx, Inc. - San Jose CA

G01R 31/28, G06F 11/00, H03L 7/00, H04L 12/28, H04B 10/00

714725, 714707, 714744, 327141, 327143, 37039562, 398155, 398158

A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are operably coupled to latch even and odd bits of a digital stream of data based on a recovered clock to produce even and odd latched bits. The detection module is operably coupled to produce a phase representative pulse stream based on the even and odd latched bits. The clock recovery module is operably coupled to produce the recovered clock based on the phase representative pulse stream. The compensating module is operably coupled to adjust biasing of the even and odd latches based on operating parameter changes of the clock and data recovery circuit. The data recovery module is operably coupled to produce recovered data from the even and odd latched bits based on the recovered clock.

7888202, Feb 15, 2011

Sep 14, 2009

12/558756

Firas N. Abughazaleh - Austin TX, US
Brian T. Brunn - Austin TX, US

Xilinx, Inc. - San Jose CA

H01L 27/108

438253, 438396, 257532

A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.

7619298, Nov 17, 2009

Mar 31, 2005

11/095812

Firas N. Abughazaleh - Austin TX, US
Brian T. Brunn - Austin TX, US

Xilinx, Inc. - San Jose CA

H01L 27/108

257532, 257516, 257535, 257306, 257E27034

A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.

7541652, Jun 2, 2009

May 5, 2004

10/839932

Firas N. Abughazaleh - Austin TX, US

XILINX, Inc. - San Jose CA

H01L 29/72

257372, 257373, 257401, 257500, 257528, 257544

An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on the substrate. The first low impedance guard ring is fabricated on the substrate to at least partially surround the well-doped blocking ring, wherein the first low impedance guard ring is operably coupled to a first circuit ground, wherein impedance of the first low impedance guard ring is substantially less than impedance of the well-doped blocking ring.

7505541, Mar 17, 2009

Apr 5, 2005

11/099865

Brian T. Brunn - Austin TX, US
Firas N. Abughazaleh - Austin TX, US

Xilinx, Inc. - San Jose CA

H04L 7/02, H03D 3/24

375360, 375376

The multi-mode phase and data detector includes a phase detector and a charge pump. A plurality of latching blocks clocked on complimentary phases of a feedback signal produces a plurality of phase and transition signals. Based on a selectable bias level, latched comparators in the latching blocks operate to detect the multi-level input data signal as it crosses a plurality of threshold levels. Logic within the multi-mode phase and data detector selects subsets of exclusive OR gates from sets of exclusive OR gates and subsets of the latching comparators to place the multi-mode phase and data detector in one of a PAM-4, NRZ, or PRML mode of operation. The logic further selects subsets of latched comparators from the plurality of parallel coupled latches to further define the mode of operation of the multi-mode phase and data detector.

6184813, Feb 6, 2001

Nov 20, 1998

9/197197

Firas N. Abughazaleh - Austin TX
Vijayakumaran V. Nair - Austin TX

Legerity, Inc. - Austin TX

H03M 166

341144

A method and apparatus is provided for synchronizing the arrival of data delivered over a first and second path. The method includes generating a first clock signal; delivering the data to the first path in response to receiving the first clock signal; delaying the first clock signal by a preselected time, wherein the first preselected time substantially corresponds to a difference in the time required for the data to propagate the first and second paths; and delivering the data to the second path in response to receiving the delayed clock signal.

7058120, Jun 6, 2006

Jan 18, 2002

10/051222

Jinghui Lu - Austin TX, US
Shahriar Rokhsaz - Austin TX, US
Stephen D. Anderson - Minnetonka MN, US
Michael A. Nix - Buda TX, US
Ahmed Younis - Austin TX, US
Michael Ren Kent - Austin TX, US
Yvette P. Lee - Austin TX, US
Firas N. Abughazaleh - Austin TX, US
Brian T. Brunn - Austin TX, US
Moises E. Robinson - Austin TX, US
Kazi S. Hossain - Austin TX, US

Xilinx, Inc. - San Jose CA

H03K 11/00, H04L 25/60, H04L 25/64

375214, 375373, 341100, 341101, 370366, 710 71

A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

5963159, Oct 5, 1999

Dec 5, 1997

8/985586

Firas N. Abughazaleh - Austin TX
Vijayakumaran V. Nair - Austin TX
Merle L. Miller - Austin TX
Michael Edward Stibila - Lake Mary FL

Advanced Micro Devices - Austin TX

H03M 118

341139

A gain control arrangement for use in analog-to-digital conversion includes a current generator that generates gain currents as a function of externally applied resistances. The gain currents are sequentially provided to the analog-to-digital converter, enabling the converter to use a single set of externally applied resistances to set differentiated gain factors in each of its channels.