FENG WANG, M.D., PH.D.
Osteopathic Medicine at Bothell Everett Hwy, Everett, WA

License number

Washington LP00041

Professional information

Dr. Feng Wang, Everett WA - MD (Doctor of Medicine)

Specialties:

Cardiology

Address:

Providence Medical Group Cardio
12800 Bothell Everett Hwy STE 270, Everett 98208
(425) 316-5490 (Phone)
Providence Medical Grp Cardio
1330 Rockefeller Ave STE 310, Everett 98201
(425) 316-5490 (Phone)

Procedures:

Cardiac Imaging

Conditions:

Arrhythmias (incl. Atrial Fibrillation), Hypertension, Mitral Valve Disease

Certifications:

Cardiovascular Disease, 2011, Internal Medicine, 2009

Awards:

Healthgrades Honor Roll

Languages:

English

Hospitals:

Providence Medical Group Cardio
12800 Bothell Everett Hwy STE 270, Everett 98208
Providence Medical Grp Cardio
1330 Rockefeller Ave STE 310, Everett 98201
Roger Williams Medical Center
825 Chalkstone Ave, Providence 02908

Feng Wang, Monroe WA

Specialties:

Internal Medicine, Cardiovascular Disease, Cardiology, Nuclear Cardiology

Work:

Monroe Clinic
14692 179Th Ave SE, Monroe, WA 98272 Mill Creek Clinic, Suite 270
12800 Bothell-Everett Hwy, Everett, WA 98208

Education:

Medical Center Of Fudan University (1993)

Multi-Stage Programmable Johnson Counter

US Patent:

6876717, Apr 5, 2005

Filed:

Aug 19, 2004

Appl. No.:

10/922193

Inventors:

Feng Wang - Portland OR, US
Keng L. Wong - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K021/00

US Classification:

377 47, 377126, 327115, 327117, 327278, 327279

Abstract:

A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stages includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.

Phase Locked Loop Circuit

US Patent:

2007015, Jul 12, 2007

Filed:

Dec 27, 2005

Appl. No.:

11/319043

Inventors:

Feng Wang - Portland OR, US
Keng Wong - Portland OR, US
Michael Rifani - Beaverton OR, US

International Classification:

H03L 7/06

US Classification:

327156000

Abstract:

A technique includes locking a locked loop circuit onto a reference clock signal. The locking includes locking the lock loop circuit onto the reference clock signal in response to a first feedback signal provided by a first feedback path and locking the locked loop circuit onto the reference clock signal in response to a second feedback signal that is provided by a second feedback path.

Multi Mode Clock Generator

US Patent:

7408420, Aug 5, 2008

Filed:

Sep 27, 2005

Appl. No.:

11/237268

Inventors:

Keng L. Wong - Portland OR, US
Feng Wang - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 7/00

US Classification:

331 49, 331177 R, 331 34

Abstract:

In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.