FENG WANG, M.D., PH.D.
Osteopathic Medicine at Bothell Everett Hwy, Everett, WA

6876717, Apr 5, 2005

Aug 19, 2004

10/922193

Feng Wang - Portland OR, US
Keng L. Wong - Portland OR, US

Intel Corporation - Santa Clara CA

H03K021/00

377 47, 377126, 327115, 327117, 327278, 327279

A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stages includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.

2007015, Jul 12, 2007

Dec 27, 2005

11/319043

Feng Wang - Portland OR, US
Keng Wong - Portland OR, US
Michael Rifani - Beaverton OR, US

H03L 7/06

327156000

A technique includes locking a locked loop circuit onto a reference clock signal. The locking includes locking the lock loop circuit onto the reference clock signal in response to a first feedback signal provided by a first feedback path and locking the locked loop circuit onto the reference clock signal in response to a second feedback signal that is provided by a second feedback path.

7408420, Aug 5, 2008

Sep 27, 2005

11/237268

Keng L. Wong - Portland OR, US
Feng Wang - Portland OR, US

Intel Corporation - Santa Clara CA

H03L 7/00

331 49, 331177 R, 331 34

In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.