FENG SHI
Pilots at Michelson Dr, Irvine, CA
License number
California A5259973
Issued Date
Aug 2015
Expiration Date
Aug 2020
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
3395 Michelson Dr, Irvine, CA 92612
Professional information
Deinterleaver And Dual-Viterbi Decoder Architecture
US Patent:
7779338, Aug 17, 2010
Filed:
Jul 21, 2006
Appl. No.:
11/490844
Inventors:
Mustafa Altintas - Irvine CA, US
Turgut Aytur - Plattsburgh NY, US
Ravishankar H. Mahadevappa - Irvine CA, US
Feng Shi - Irvine CA, US
Stephan ten Brink - Irvine CA, US
Ran Yan - Holmdel NJ, US
Turgut Aytur - Plattsburgh NY, US
Ravishankar H. Mahadevappa - Irvine CA, US
Feng Shi - Irvine CA, US
Stephan ten Brink - Irvine CA, US
Ran Yan - Holmdel NJ, US
Assignee:
Realtek Semiconductor Corp. - Hsinchu
International Classification:
H03M 13/03
US Classification:
714795
Abstract:
Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.
Detection And Removal Of Hazards During Optimization Of Logic Circuits
US Patent:
8392858, Mar 5, 2013
Filed:
Mar 6, 2009
Appl. No.:
12/399119
Inventors:
Feng Shi - Irvine CA, US
Assignee:
Skyworks Solutions, Inc. - Woburn MA
International Classification:
G06F 17/50
US Classification:
716106
Abstract:
A method of generating a hazard-free representation of a logic circuit that can leverage the powerful and mature synchronous-circuit CAD synthesis tools. In a representative embodiment of the method, an initial representation of a specified asynchronous logic circuit is synthesized using one of such CAD tools. The initial representation is then analyzed to identify hazardous transitions and modified, e. g. , by iteratively inserting additional logic aimed at preventing the identified hazardous transitions from producing glitches, until a hazard-free representation of the specified asynchronous logic circuit is produced.