Eugene Saghi
Engineers at Smoke Rdg Dr, Colorado Springs, CO

2013026, Oct 3, 2013

Mar 30, 2012

13/434940

Eugene Saghi - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US
Joshua P. Sinykin - Shrewsbury MA, US

G01R 31/3177, G06F 11/25

714744, 714E11155

Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.

2013025, Oct 3, 2013

Mar 30, 2012

13/434954

Eugene Saghi - Colorado Springs CO, US
Paul J. Smith - Colorado Springs CO, US
Joshua P. Sinykin - Shrewsbury MA, US
Jeffrey K. Whitt - Colorado Springs CO, US

H03K 17/00

327403

Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit.

2013026, Oct 3, 2013

Mar 30, 2012

13/434962

Paul J. Smith - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Douglas J. Saxon - Colorado Springs CO, US
Joshua P. Sinykin - Shrewsbury MA, US

G06F 19/00, G06F 11/25, G01R 31/3177

714744, 702120, 714E11155

Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.

7646668, Jan 12, 2010

Mar 31, 2008

12/058964

John Udell - Colorado Springs CO, US
Richard Solomon - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US

LSI Corporation - Milpitas CA

G11C 8/00

365236, 365193, 3652331

Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.

2014004, Feb 6, 2014

Aug 6, 2012

13/567712

Eugene Saghi - Colorado Springs CO, US
Richard Solomon - Colorado Springs CO, US

LSI CORPORATION - Milpitas CA

G06F 11/34

714 45, 714E11189

Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.

8077620, Dec 13, 2011

Oct 8, 2008

12/247845

Richard Solomon - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US

LSI Corporation - Milpitas CA

H04J 3/14

370235, 3702351, 370252

Methods and systems for processing a second request before processing of a first request has completed. The first request is associated with a first flow control credit type, and the second request is associated with a second flow control credit type. After a period of time, the second request is selected for processing based on the first flow control credit type and the second flow control credit type.

8108574, Jan 31, 2012

Oct 8, 2008

12/247769

John C. Udell - Colorado Springs CO, US
Richard Solomon - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US

LSI Corporation - Milpitas CA

G06F 13/00, G06F 11/00

710 52, 714 49

Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.

8176207, May 8, 2012

Mar 26, 2008

12/079371

Richard I. Solomon - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Garret Davey - Colorado Springs CO, US

LSI Corporation - Milpitas CA

G06F 3/00, G06F 12/06

710 2, 710 8, 710 9, 710 10, 711 2, 711202, 718104

An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

2010001, Jan 14, 2010

Jul 11, 2008

12/171383

Eugene Saghi - Colorado Springs CO, US

LSI CORPORATION - Milpitas CA

G06F 13/36

710314

A method for determining when all data has been sent for a given PCI Express bus command issued by a backend entity of a PCI Express bus device, by setting a PCI Express bus packet header tag field of a PCI Express bus packet to indicate a backend entity that originated the PCI Express bus command and whether the PCI Express bus packet is a last packet of the PCI Express bus command, and then inspecting the PCI Express bus packet header tag field of the PCI Express bus packet to determine whether the PCI Express bus packet is the last packet of the PCI Express bus command.

7237043, Jun 26, 2007

Nov 21, 2003

10/718937

Richard L. Solomon - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Amanda White - Colorado Springs CO, US

LSI Corporation - Milpitas CA

G06F 3/00, G06F 9/26, G06F 13/00, G06F 5/00

710 6, 710 5, 710 36, 710 39, 710 40

A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.