MR. ERIC SETH WEBB, MD
Marriage and Family Therapists at Fern Valley Rd, Medford, OR

License number
Oregon 17110
Category
Osteopathic Medicine
Type
Family Medicine
Address
Address 2
205 Fern Valley Rd STE A, Medford, OR 97535
PO Box 3158, Portland, OR 97208
Phone
(541) 535-1274
(541) 535-6973 (Fax)

Personal information

See more information about ERIC SETH WEBB at radaris.com
Name
Address
Phone
Eric Webb
585 Lincoln Rd, Grants Pass, OR 97526
(541) 476-7769
Eric Webb, age 66
545 Winters Way, Talent, OR 97540
Eric R Webb, age 51
1543 Harlandale Ave SE, Salem, OR 97306
Eric R Webb, age 51
1947 K St, Grants Pass, OR 97526
(541) 472-9230
Eric R Webb, age 51
1947 K St, Grants Pass, OR 97526

Professional information

See more information about ERIC SETH WEBB at trustoria.com
Eric Webb Photo 1
Sr. Vp At Capsa Solutions

Sr. Vp At Capsa Solutions

Position:
Sr. Vice President at Capsa Solutions at Capsa Solutions
Location:
Portland, Oregon Area
Industry:
Executive Office
Work:
Capsa Solutions since Nov 2008 - Sr. Vice President at Capsa Solutions Warn Industries Mar 2005 - Nov 2008 - Director of Engineering Connor Manufacturing Services Sep 1997 - Mar 2005 - Director of Engineering and Business Development
Education:
Washington State University 1998 - 2001
MBA, Business
Purdue University 1990 - 1995
BSME, Mechanical Engineering


Eric Webb Photo 2
Moses Lake Industries

Moses Lake Industries

Position:
Manager at Moses Lake Industries
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Moses Lake Industries since Jul 2008 - Manager Novellus Systems Nov 2007 - Jun 2008 - Process Engineering Manager Novellus Systems Feb 2001 - Nov 2007 - Process Engineer
Education:
University of Illinois at Urbana-Champaign 1995 - 2000
Ph. D., Chemical Engineering, Electrochemisty, Electrochemical Engineering
Oregon State University 1990 - 1995
B.S., Chemical Engineering


Eric Seth Webb Photo 3
Eric Seth Webb, Medford OR

Eric Seth Webb, Medford OR

Specialties:
Family Medicine, Internal Medicine
Work:
Providence Medford Medical Center
1698 E Mcandrews Rd, Medford, OR 97504 Providence Medical Group
205 Fern Valley Rd, Phoenix, OR 97535 Providence Medical Group Phoenix Family Practice
205 Fern Valley Rd, Phoenix, OR 97535
Education:
Medical University of South Carolina (1986)


Eric S Webb Photo 4
Dr. Eric S Webb, Medford OR - MD (Doctor of Medicine)

Dr. Eric S Webb, Medford OR - MD (Doctor of Medicine)

Specialties:
Family Medicine
Address:
1698 E Mcandrews Rd, Medford 97504
Providence Medical Group
205 Fern Valley Rd SUITE A, Phoenix 97535
(541) 535-1274 (Phone)
Certifications:
Family Practice, 2013
Awards:
Healthgrades Honor Roll
Languages:
English
Hospitals:
1698 E Mcandrews Rd, Medford 97504
Providence Medical Group
205 Fern Valley Rd SUITE A, Phoenix 97535
Asante Rogue Regional Medical Center
2825 East Barnett Rd, Medford 97504
Providence Medical Center
1200 Providence Rd, Wayne 68787
Education:
Medical School
Medical University Of South Carolina
Graduated: 1986
University Ky
Graduated: 1989


Eric Webb Photo 5
Fabrication Of Semiconductor Interconnect Structure

Fabrication Of Semiconductor Interconnect Structure

US Patent:
8481432, Jul 9, 2013
Filed:
May 26, 2011
Appl. No.:
13/116963
Inventors:
Steven T. Mayer - Lake Oswego OR, US
Daniel A. Koos - Portland OR, US
Eric Webb - Tigard OR, US
Assignee:
Novellus Systems, Inc. - Fremont CA
International Classification:
H01L 21/302
US Classification:
438754, 438745, 438747, 216100
Abstract:
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.


Eric Webb Photo 6
Fabrication Of Semiconductor Interconnect Structure

Fabrication Of Semiconductor Interconnect Structure

US Patent:
7972970, Jul 5, 2011
Filed:
Jul 30, 2007
Appl. No.:
11/888312
Inventors:
Steven T. Mayer - Lake Oswego OR, US
Daniel A. Koos - Portland OR, US
Eric Webb - Tigard OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/302
US Classification:
438754, 438745, 216100
Abstract:
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.


Eric Webb Photo 7
Topography Reduction And Control By Selective Accelerator Removal

Topography Reduction And Control By Selective Accelerator Removal

US Patent:
8158532, Apr 17, 2012
Filed:
Nov 20, 2006
Appl. No.:
11/602128
Inventors:
Steven T. Mayer - Lake Oswego OR, US
Mark L. Rea - Tigard OR, US
Richard S. Hill - Atherton CA, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Eric G. Webb - Tigard OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/302
US Classification:
438754, 438692, 438745, 438759, 216105
Abstract:
Plating accelerator is applied selectively to a substantially-unfilled wide (e. g. , low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e. g. , high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.


Eric Webb Photo 8
Photoresist-Free Metal Deposition

Photoresist-Free Metal Deposition

US Patent:
7947163, May 24, 2011
Filed:
Aug 6, 2007
Appl. No.:
11/890541
Inventors:
Steven T. Mayer - Lake Oswego OR, US
John Stephen Drewery - Santa Clara CA, US
Eric G. Webb - Tigard OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C25F 3/14
US Classification:
205667, 205668
Abstract:
Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.


Eric Webb Photo 9
Photoresist-Free Metal Deposition

Photoresist-Free Metal Deposition

US Patent:
8500985, Aug 6, 2013
Filed:
Jul 13, 2007
Appl. No.:
11/827800
Inventors:
Steven T. Mayer - Lake Oswego OR, US
John Stephen Drewery - Santa Clara CA, US
Eric G. Webb - Tigard OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C25D 5/34, C25D 5/00, C25D 5/02, B05D 5/00
US Classification:
205205, 205112, 205206, 205136, 427256
Abstract:
Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.


Eric Webb Photo 10
Marketing At Agik, Inc.

Marketing At Agik, Inc.

Position:
Marketing at AGIK, Inc.
Location:
Portland, Oregon Area
Industry:
Online Media
Work:
AGIK, Inc. - Marketing