Inventors:
Eric R. Miller - Colorado Springs CO
Stephen R. Moon - Colorado Springs CO
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 2176
US Classification:
438427, 438438, 438700, 438973, 257521
Abstract:
A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon wafer at a 45 degree angle to the ( ) plane of the wafer. This is achieved by moving the primary flat of the wafer to the ( ) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several ( ) planes, so that stresses do not propagate along any one single ( ) plane. The trenches are then filled with an insulative material, such as oxide.