Eric A Dale
Electrician at Pitchfork Dr, Colorado Springs, CO
License number
Colorado 951184
Issued Date
Oct 14, 1995
Renew Date
Oct 14, 1995
Expiration Date
Feb 28, 2001
Type
Electrical Apprentice
Address
Address
6470 Pitchfork Dr, Colorado Springs, CO 80922
Personal information
See more information about Eric A Dale at radaris.comName
Address
Phone
5700 Cherry Cir, Greenwood Vlg, CO 80121
2272 S Meade St, Denver, CO 80219
9 Elk Path, Manitou Spgs, CO 80829
1310 S Harlan St, Lakewood, CO 80232
16561 W Ellsworth Ave, Golden, CO 80401
Professional information
Director - Financial Planning &Amp; Analysis
Position:
Director - Financial Planning & Analysis at Westmoreland Coal Company
Location:
Colorado Springs, Colorado Area
Industry:
Mining & Metals
Work:
Westmoreland Coal Company
- Englewood, CO since Apr 2010
-
Director - Financial Planning & Analysis
Xcel Energy
Oct 2008 - Apr 2010
-
Principal Financial Consultant
Colorado Springs Utilities
Jul 2005 - Oct 2008
-
Lead Financial/Budget Analyst
Anthem
Mar 2004 - Jul 2005
-
Senior Financial Analyst
Centura Health
Mar 2000 - Mar 2004
-
Senior Financial Analyst
Education:
Xavier University 1997 - 2000
Master of Health Services Administration, Managed Care; Finance & Accounting Xavier University - School of Business Administration 1997 - 1999
Master of Business Administration, Finance; Marketing State University of New York College at Fredonia 1993 - 1997
Bachelor of Science, Sociology, Health Services Administration
Master of Health Services Administration, Managed Care; Finance & Accounting Xavier University - School of Business Administration 1997 - 1999
Master of Business Administration, Finance; Marketing State University of New York College at Fredonia 1993 - 1997
Bachelor of Science, Sociology, Health Services Administration
Staff Test Engineer At Cypress Semiconductor
Position:
Staff Test Engineer at Cypress Semiconductor
Location:
Colorado Springs, Colorado Area
Industry:
Semiconductors
Work:
Cypress Semiconductor
- Colorado Springs, Colorado Area since Nov 2012
-
Staff Test Engineer
Ramtron
- Colorado Springs, Colorado Area Feb 1996 - Nov 2012
-
Lead Test Engineer
Process And Structure For Masking Integrated Capacitors Of Particular Utility For Ferroelectric Memory Integrated Circuits
US Patent:
2002011, Aug 29, 2002
Filed:
Feb 28, 2001
Appl. No.:
09/797394
Inventors:
Shan Sun - Colorado Springs CO, US
George Hickert - Colorado Springs CO, US
Diana Johnson - Colorado Springs CO, US
John Ortega - Boulder CO, US
Eric Dale - Colorado Springs CO, US
Masahisa Ueda - Suyama Susono-shi, JP
George Hickert - Colorado Springs CO, US
Diana Johnson - Colorado Springs CO, US
John Ortega - Boulder CO, US
Eric Dale - Colorado Springs CO, US
Masahisa Ueda - Suyama Susono-shi, JP
International Classification:
H01L029/76, H01L029/94, H01L031/062, H01L031/113, H01L031/119, H01L027/108, H01L021/20
US Classification:
257/295000, 257/296000, 438/396000
Abstract:
A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.
Process And Structure For Masking Integrated Capacitors Of Particular Utility For Ferroelectric Memory Integrated Circuits
US Patent:
2003007, Apr 17, 2003
Filed:
Oct 30, 2002
Appl. No.:
10/285140
Inventors:
Shan Sun - Colorado Springs CO, US
George Hickert - Colorado Springs CO, US
Diana Johnson - Colorado Springs CO, US
John Ortega - Boulder CO, US
Eric Dale - Colorado Springs CO, US
Masahisa Ueda - Suyama Susono-shi, JP
George Hickert - Colorado Springs CO, US
Diana Johnson - Colorado Springs CO, US
John Ortega - Boulder CO, US
Eric Dale - Colorado Springs CO, US
Masahisa Ueda - Suyama Susono-shi, JP
International Classification:
H01L027/108, H01L031/119, H01L031/113, H01L021/20, H01L031/062, H01L029/76, H01L029/94, H01L021/8242
US Classification:
257/295000, 257/306000, 257/310000, 438/240000, 438/396000
Abstract:
A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.