Inventors:
Susan J. Eggers - Seattle WA, US
Luis Ceze - Seattle WA, US
Emily Fortuna - Seattle WA, US
Owen Anderson - San Jose CA, US
Assignee:
University of Washington through its Center for Commercialization - Seattle WA
International Classification:
G06F 11/36
Abstract:
Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.