EDWARD MARTIN MCCOMBS, JR
Pilots at Cyn Blf Ct, Austin, TX
License number
Texas A4716890
Issued Date
Oct 2016
Expiration Date
Oct 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
14420 Canyon Bluff Ct, Austin, TX 78734
Personal information
See more information about EDWARD MARTIN MCCOMBS at radaris.comName
Address
Phone
4937 Courtside Dr APT 125, Irving, TX 75038
Irving, TX
12813 Rush Creek Ln, Austin, TX 78732
4212 Summercrest Loop, Round Rock, TX 78681
7308 Scenic Brook Dr, Austin, TX 78736
Professional information
Senior Circuit Designer At Apple Inc.
Location:
Austin, Texas Area
Industry:
Computer Hardware
Memory Including A Reduced Leakage Wordline Driver
US Patent:
2013011, May 2, 2013
Filed:
Nov 1, 2011
Appl. No.:
13/286351
Inventors:
Edward M. McCombs - Austin TX, US
Stephen C. Horne - Austin TX, US
Alexander E. Runas - Austin TX, US
Daniel C. Chow - Austin TX, US
Stephen C. Horne - Austin TX, US
Alexander E. Runas - Austin TX, US
Daniel C. Chow - Austin TX, US
International Classification:
G11C 5/14, G06F 12/08
US Classification:
711118, 365227, 711E12017
Abstract:
A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
Power Estimation In An Integrated Circuit Design Flow
US Patent:
2012020, Aug 9, 2012
Filed:
Jul 14, 2011
Appl. No.:
13/183335
Inventors:
Jason A. Frerich - Bastrop TX, US
Christopher M. Goertz - Red Rock TX, US
Edward M. McCombs - Austin TX, US
Christopher M. Goertz - Red Rock TX, US
Edward M. McCombs - Austin TX, US
International Classification:
G06F 19/00
US Classification:
702 60
Abstract:
Power estimates for an integrated circuit may be obtained without having to individually enter monitor statements at hierarchical levels in a design. The current, or consumed power may be considered at the transistor level throughout the entire circuit, even when the circuit is divided into hierarchical modules. Current, or power measurements may be obtained after a circuit has been synthesized and an extracted transistor-level netlist has been created. Separate netlists may be created for different modules, and estimate results collected from the different modules, since current measurements are performed at the transistor level. To accurately estimate the power consumption, the current flowing through transistors that are connected to power rails in the netlist may be measured during circuit simulation. This may be accomplished via measurement statements created for these transistors, and placed in a simulation input file, by a script or program, for example. Only the currents flowing through these transistors need to be measured to account for all the current provided from the power sources in the design.
Integrated Circuit Including Pulse Control Logic Having Shared Gating Control
US Patent:
2013010, May 2, 2013
Filed:
Dec 17, 2012
Appl. No.:
13/717396
Inventors:
Apple Inc. - Cupertino CA, US
Edward M. McCombs - Austin TX, US
Edward M. McCombs - Austin TX, US
Assignee:
APPLE INC. - Cupertino CA
International Classification:
H03K 19/096
US Classification:
326 93
Abstract:
An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.
Memory Having Isolation Units For Isolating Storage Arrays From A Shared I/O During Retention Mode Operation
US Patent:
8570824, Oct 29, 2013
Filed:
Jan 24, 2012
Appl. No.:
13/356786
Inventors:
Edward M. McCombs - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G11C 7/02
US Classification:
365207, 365226, 36518911
Abstract:
A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
Integrated Circuit Including Pulse Control Logic Having Shared Gating Control
US Patent:
2012012, May 17, 2012
Filed:
Apr 29, 2011
Appl. No.:
13/097206
Inventors:
Edward M. McCombs - Austin TX, US
International Classification:
H04L 7/00, H04W 24/00
US Classification:
375224, 375354
Abstract:
An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.
Memory With A Shared I/O Including An Output Data Latch Having An Integrated Clamp
US Patent:
8553472, Oct 8, 2013
Filed:
Dec 5, 2011
Appl. No.:
13/311340
Inventors:
Edward M. McCombs - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G11C 7/10
US Classification:
36518905, 365226, 365229, 365227, 36523008
Abstract:
A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
Mechanism For Peak Power Management In A Memory
US Patent:
8649240, Feb 11, 2014
Filed:
Feb 18, 2013
Appl. No.:
13/769542
Inventors:
Edward M. McCombs - Austin TX, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G11C 8/00
US Classification:
36523003, 36523006, 365194
Abstract:
A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.
Memory Device Including A Retention Voltage Resistor
US Patent:
2013013, May 30, 2013
Filed:
Nov 29, 2011
Appl. No.:
13/305796
Inventors:
Edward M. McCombs - Austin TX, US
Kenneth W. Jones - Austin TX, US
Kenneth W. Jones - Austin TX, US
International Classification:
G11C 5/14
US Classification:
365226
Abstract:
A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode.
Method For Optimizing Sense Amplifier Timing
US Patent:
2014003, Jan 30, 2014
Filed:
Jul 26, 2012
Appl. No.:
13/558976
Inventors:
Edward M. McCombs - Austin TX, US
Alexander E. Runas - Austin TX, US
Michael E. Runas - McKinney TX, US
Alexander E. Runas - Austin TX, US
Michael E. Runas - McKinney TX, US
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
Embodiments of a method are disclosed that may allow for the optimization of a memory circuit design parameter. The method may include the statistical simulation of one or more operational parameters of the memory circuit. Probabilities of the operational parameters achieving pre-defined probability goals may be used to optimize the memory circuit design parameter.