Inventors:
Edward C. Chang - San Francisco CA, US
Deirdre McGlashan - San Francisco CA, US
Meimei Chang - San Francisco CA, US
International Classification:
H03B 21/00
Abstract:
A frequency synthesizer and a method for constructing the same by using the architecture of digital process frequency loop (DPFL) are disclosed. The DPFL frequency synthesizer with the DPFL architecture includes a reference frequency divider counter, an output divider counter, a processor, a memory, a digital to analog converter (DAC), and a voltage Control Oscillator (VCO). The method uses the processor to perform the signal processing to correct the output frequency of the VCO in the frequency domain. The memory stores the nonlinear characteristics of the VCO such that the synthesizer is completely controlled, no uncertain frequency being captured during process, and the frequency resolution of the synthesizer is programmable.