EDMUND BURTON MINSHALL
Pilots at Tooze Rd, Sherwood, OR
License number
Oregon A2299789
Issued Date
Jul 2016
Expiration Date
Jul 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
12491 SW Tooze Rd, Sherwood, OR 97140
Personal information
See more information about EDMUND BURTON MINSHALL at radaris.comName
Address
Phone
12491 SW Tooze Rd, Sherwood, OR 97140
12491 Tooze Rd, Sherwood, OR 97140
12491 SW Tooze Rd, Sherwood, OR 97140
Professional information
Electroless Copper Deposition Apparatus
US Patent:
6815349, Nov 9, 2004
Filed:
Oct 18, 2002
Appl. No.:
10/274837
Inventors:
Edmund B. Minshall - Sherwood OR
Kevin Biggs - Tualatin OR
R. Marshall Stowell - Wilsonville OR
Wayne Fetters - Canby OR
Kevin Biggs - Tualatin OR
R. Marshall Stowell - Wilsonville OR
Wayne Fetters - Canby OR
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 2144
US Classification:
438678
Abstract:
An apparatus for holding work pieces during electroless plating has certain improved features designed for use at relatively high temperatures (e. g. , at least about 50 degrees C. ). Cup and cone components of a âclamshellâ apparatus that engage a work piece are made from dimensionally stable materials with relatively low coefficients of thermal expansion. Further, O-rings are removed from positions that come in contact with the work piece. This avoids the difficulty caused by O-rings sticking to work piece surfaces during high temperature processing. In place of the O-ring, a cantilever member is provided on the portion of the cone that contacts the work piece. Still further, the apparatus makes use of a heat transfer system for controlling the temperature of the work piece backside during plating.
Electrochemical Treatment Of Integrated Circuit Substrates Using Concentric Anodes And Variable Field Shaping Elements
US Patent:
2002019, Dec 26, 2002
Filed:
Apr 4, 2002
Appl. No.:
10/116077
Inventors:
Steven Mayer - Lake Oswego OR, US
Timothy Cleary - Portland OR, US
Michael Janicki - West Linn OR, US
Edmund Minshall - Sherwood OR, US
Thomas Ponnuswamy - Tulatin OR, US
Timothy Cleary - Portland OR, US
Michael Janicki - West Linn OR, US
Edmund Minshall - Sherwood OR, US
Thomas Ponnuswamy - Tulatin OR, US
International Classification:
C25B015/00, C25C007/00, C25B009/00
US Classification:
205/687000, 204/232000, 204/242000
Abstract:
An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.
Capping Before Barrier-Removal Ic Fabrication Method
US Patent:
7605082, Oct 20, 2009
Filed:
Oct 13, 2005
Appl. No.:
11/251353
Inventors:
Jonathan D. Reid - Sherwood OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/44
US Classification:
438678, 257E21076, 257E21174
Abstract:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e. g. , copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e. g. , overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
Small-Volume Electroless Plating Cell
US Patent:
7690324, Apr 6, 2010
Filed:
Aug 9, 2005
Appl. No.:
11/200338
Inventors:
Jingbin Feng - Lake Oswego OR, US
Steven T. Mayer - Lake Oswego OR, US
Daniel Mark Dinneen - Portland OR, US
Edmund B. Minshall - Sherwood OR, US
Christopher M. Bartlett - Beaverton OR, US
Eric G. Webb - West Linn OR, US
R. Marshall Stowell - Wilsonville OR, US
Mark T. Winslow - Camas WA, US
Avishai Kepten - Lake Oswego OR, US
Norman D. Kaplan - Portland OR, US
Richard K. Lyons - Sandy OR, US
John B. Alexy - West Linn OR, US
Steven T. Mayer - Lake Oswego OR, US
Daniel Mark Dinneen - Portland OR, US
Edmund B. Minshall - Sherwood OR, US
Christopher M. Bartlett - Beaverton OR, US
Eric G. Webb - West Linn OR, US
R. Marshall Stowell - Wilsonville OR, US
Mark T. Winslow - Camas WA, US
Avishai Kepten - Lake Oswego OR, US
Norman D. Kaplan - Portland OR, US
Richard K. Lyons - Sandy OR, US
John B. Alexy - West Linn OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
B05C 11/02
US Classification:
118 52, 118731, 118429, 118423
Abstract:
During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being injected into the container. Preferably, the chemical composition, temperature, and other properties of fluid in the thin enclosed fluid-treatment volume are dynamically variable. A rinse shield and a rinse nozzle are located above the container. A carrier/wafer assembly in a rinse position substantially closes the top of the rinse shield.
Liquid Treatment Using Thin Liquid Layer
US Patent:
2004006, Apr 8, 2004
Filed:
Jun 30, 2003
Appl. No.:
10/609518
Inventors:
Steven Mayer - Lake Oswego OR, US
Jonathan Reid - Sherwood OR, US
Timothy Cleary - Portland OR, US
Edmund Minshall - Sherwood OR, US
R. Stowell - Wilsonville OR, US
Heung Park - Wilsonville OR, US
Jonathan Reid - Sherwood OR, US
Timothy Cleary - Portland OR, US
Edmund Minshall - Sherwood OR, US
R. Stowell - Wilsonville OR, US
Heung Park - Wilsonville OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C25D017/00
US Classification:
204/198000
Abstract:
A treating head having a treating surface and a substrate treatment surface define a thin fluid gap that is filled with reactant liquid to form a thin liquid layer on the substrate for conducting a liquid chemical reaction treatment or other liquid treatment of the substrate. The thin liquid layer has a volume in a range of about from 50 ml to 500 ml. Preferably, the chemical composition, temperature, and other properties of liquid in the thin liquid layer are dynamically variable.
Capping Before Barrier-Removal Ic Fabrication Method
US Patent:
7811925, Oct 12, 2010
Filed:
Jul 31, 2008
Appl. No.:
12/184145
Inventors:
Jonathan D. Reid - Sherwood OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/302, H01L 21/461, B24B 7/00
US Classification:
438622, 451 64, 451461, 15634512, 414935, 438690
Abstract:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e. g. , copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e. g. , overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
Electroless Plating-Liquid System
US Patent:
8257781, Sep 4, 2012
Filed:
Aug 11, 2005
Appl. No.:
11/201709
Inventors:
Eric G. Webb - West Linn OR, US
Steven T. Mayer - Lake Oswego OR, US
David Mark Dinneen - Portland OR, US
Edmund B. Minshall - Sherwood OR, US
Christopher M. Bartlett - Beaverton OR, US
R. Marshall Stowell - Wilsonville OR, US
Mark T. Winslow - Camas WA, US
Avishai Kepten - Lake Oswego OR, US
Jingbin Feng - Lake Oswego OR, US
Norman D. Kaplan - Portland OR, US
Richard K. Lyons - Sandy OR, US
John B. Alexy - West Linn OR, US
Steven T. Mayer - Lake Oswego OR, US
David Mark Dinneen - Portland OR, US
Edmund B. Minshall - Sherwood OR, US
Christopher M. Bartlett - Beaverton OR, US
R. Marshall Stowell - Wilsonville OR, US
Mark T. Winslow - Camas WA, US
Avishai Kepten - Lake Oswego OR, US
Jingbin Feng - Lake Oswego OR, US
Norman D. Kaplan - Portland OR, US
Richard K. Lyons - Sandy OR, US
John B. Alexy - West Linn OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C23C 14/00
US Classification:
427 979, 427 995
Abstract:
A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.
Capping Before Barrier-Removal Ic Fabrication Method
US Patent:
8415261, Apr 9, 2013
Filed:
Oct 11, 2011
Appl. No.:
13/270809
Inventors:
Jonathan D. Reid - Sherwood OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Assignee:
Novellus Systems, Inc. - Fremont CA
International Classification:
H01L 21/00, B01J 19/12
US Classification:
438800, 204193
Abstract:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e. g. , copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e. g. , overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
Capping Before Barrier-Removal Ic Fabrication Method
US Patent:
8043958, Oct 25, 2011
Filed:
Sep 3, 2010
Appl. No.:
12/875857
Inventors:
Jonathan D. Reid - Sherwood OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Eric G. Webb - West Linn OR, US
Edmund B. Minshall - Sherwood OR, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Steven T. Mayer - Lake Oswego OR, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/302, H01L 21/461, B24B 7/00
US Classification:
438622, 451 64, 15634512
Abstract:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e. g. , copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e. g. , overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
Compound Angled Pad End-Effector
US Patent:
7048316, May 23, 2006
Filed:
Jul 12, 2002
Appl. No.:
10/194529
Inventors:
Richard Blank - Sunnyvale CA, US
Simon Chan - Campbell CA, US
Edmund Minshall - Sherwood OR, US
Peter Woytowitz - Mountain View CA, US
Simon Chan - Campbell CA, US
Edmund Minshall - Sherwood OR, US
Peter Woytowitz - Mountain View CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
B66C 1/00
US Classification:
294 11, 294902, 901 30, 414941, 414935
Abstract:
This invention provides a method and a support device for a wafer transfer process which has a first vertical, second horizontal and third compound angled surfaces, as well as a pair of sidewalls all contiguously connected to one another. The third surface has at least two angled receiving surfaces whereby one of such angled receiving surfaces has a small angle of incline for initially receiving and delivering a wafer. The other angled receiving surface has a steep angle of incline for effectively receiving, holding and transporting a semiconductor wafer by increasing an effective coefficient of friction of the wafer to provide a secure resting point for such wafer during a transfer process while simultaneously increasing the speed thereof. Furthermore, a hole may be provided in the support device for attaching the support device, or a plurality of support devices having holes, to an end-effector.