EDGAR R CASSINELLI
Broker in Marlboro, MA
License number
Massachusetts 84054
Issued Date
May 1, 1973
Expiration Date
Feb 27, 1982
Type
Broker
Address
Address
Marlboro, MA 01752
Personal information
See more information about EDGAR R CASSINELLI at radaris.comName
Address
Phone
209 Kings Grant Rd, Marlborough, MA 01752
209 Kings Grant Rd, Marlborough, MA 01752
Professional information
See more information about EDGAR R CASSINELLI at trustoria.com
Method And Apparatus For Providing A Carrier Termination For A Semiconductor Package
Method And Apparatus For Providing A Carrier Termination For A Semiconductor Package
US Patent:
4652065, Mar 24, 1987
Filed:
Feb 14, 1985
Appl. No.:
6/701575
Inventors:
Edgar R. Cassinelli - Marlboro MA
Assignee:
Prime Computer, Inc. - Natick MA
International Classification:
H01R 909
US Classification:
339 17CF
Abstract:
A semiconductor termination socket for use with a printed wiring board has a mounting socket base for attachment to the board and plural pin socket receiving elements in the base for connecting to leads of a semiconductor chip package which will be removably inserted into the socket. The socket further has electrical components fabricated within the socket base for connecting a pin of the socket and a termination potential. The electrical components are preferably fabricated using planar technology so that the socket becomes, in essence, a printed wiring board. The semiconductor packages can be of any configuration including, for example, 149 pin grid array packages. If more than one layer of component circuitry is needed, a plurality of layers can be embedded within the mounting socket.
Semiconductor Chip Carrier Package
Semiconductor Chip Carrier Package
US Patent:
4860165, Aug 22, 1989
Filed:
Apr 27, 1988
Appl. No.:
7/187057
Inventors:
Edgar Cassinelli - Marlboro MA
Assignee:
Prime Computer, Inc. - Natick MA
International Classification:
H05K 720
US Classification:
361388
Abstract:
A semiconductor chip carrier package formed of a multi-layer circuit board having mounted therein a semiconductor chip support pad. The multi-layer circuit board is comprised of separate dielectric boards defining multiple conductive run layers including a signal layer and a plurality of power layers. A pluralilty of pins supported from the circuit board extending from one side thereof and including signal pins and power pins. The power pins are disposed peripherally outside of the signal pins. Means are provided for conductively connecting leads of the semiconductor chip to corresponding conductive runs of the signal and power layers.