Earl Eugene Swartzlander
Engineers in Austin, TX

2007013, Jun 14, 2007

Dec 12, 2005

11/299974

Moises Robinson - Austin TX, US
Marwan Hassoun - Davis CA, US
Earl Swartzlander - Austin TX, US

Xilinx, Inc. - San Jose CA

H03L 7/06

327156000

A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump () provides a current signal () that is first conducted by a resistor () of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor () of the RC network from node (). A second current path multiplies the current conducted by capacitor () by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor ().

2007021, Sep 13, 2007

Mar 8, 2006

11/370783

Earl Swartzlander - Austin TX, US

G06F 7/38

708490000

The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors. The previously described shortcoming of the two's complement system are corrected in the present invention is a number system described as the negative two's complement system. In the negative two's complement system a n-bit number, A, has a sign bit, a, and n−1 fractional bits, a, a, . . . , a. The value of an n-bit fractional negative two's complement number is:

2005016, Jul 21, 2005

Nov 2, 2004

10/979775

Earl Swartzlander - Austin TX, US
Ayman Moustafa El-Khashab - Austin TX, US

G06F015/00

708404000

A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline N point {square root}{square root over (N)} point fast Fourier transform modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFT, the modular pipeline FFT maintains the bandwidth existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.

2008025, Oct 16, 2008

Apr 9, 2008

12/100202

Eric Quinnell - Austin TX, US
Earl E. Swartzlander - Austin TX, US
Carl Lemonds - Austin TX, US

G06F 7/483

708501

A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.

2008025, Oct 16, 2008

Apr 9, 2008

12/082127

Eric Quinnell - Austin TX, US
Earl E. Swartzlander - Austin TX, US
Carl Lemonds - Austin TX, US

G06F 5/01

708209

A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.

2008012, Jun 5, 2008

Nov 29, 2007

11/946932

Giri N.K. Rangan - Austin TX, US
Earl E. Swartzlander - Austin TX, US

H03B 5/24, H03K 3/03

331 57

A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.