DUNG D NGUYEN, M.D.
Osteopathic Medicine at Mopac, Austin, TX

8347068, Jan 1, 2013

Apr 4, 2007

11/696363

Richard James Eickemeyer - Rochester MN, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 9/30

712229, 712217

A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

2003018, Sep 25, 2003

Mar 21, 2002

10/104728

Hung Le - Austin TX, US
Dung Nguyen - Austin TX, US
Albert Williams - Austin TX, US
Raymond Yeung - Austin TX, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G06F009/00

712/216000, 712/225000

A method of handling instructions in a load/store unit of a processor by dispatching instructions to the load/store unit, filling all physical entries of a reorder queue with tags corresponding to the instructions, and further dispatching one or more additional instructions to the load/store unit while all of the physical entries in the reorder queue are still full, i.e., still contain tags for uncompleted instructions. The invention may be implemented in either a load reorder queue or a store reorder queue. Multiple logical instruction tags are assigned in a count greater than the number of physical entries in the reorder queue. Of the multiple logical instruction tags assigned to a single one of the physical entries in the reorder queue, only the tag for the oldest instruction is allowed to execute. At least one virtual bit (V) is provided to tag allocations for the load/store unit. This Vbit is flipped when a corresponding tag allocation wraps. The most significant bit of a given logical instruction tag is compared with the Vbit to determine whether the given logical instruction tag is valid, i.e., is actually stored in a physical entry of the reorder queue.

6275918, Aug 14, 2001

Mar 16, 1999

9/268307

William Elton Burky - Austin TX
Peter Steven Lenk - Austin TX
Dung Quoc Nguyen - Austin TX
David Andrew Schroter - Round Rock TX
Shih-Hsiung Stephen Tung - Austin TX
Michael Thomas Vaden - Austin TX

International Business Machines Corporation - Armonk NY

G06F 934

711213

A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.

6298435, Oct 2, 2001

Apr 16, 1996

8/633267

Kin Shing Chan - Austin TX
Hung Qui Le - Austin TX
Dung Quoc Nguyen - Austin TX

International Business Machines Corporation - Armonk NY

G06F 930

712217

A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the physical rename registers may not yet be available. These virtual rename buffers are assigned by a buffer pointer assignment table. A virtual bit implemented along with each of the physical rename registers is flipped when an instruction corresponding to the entry stored within a particular physical rename register is completed and the result written to the architected register. Thus, at dispatch time, rename registers are assigned as if there were more rename buffers than there existed physical rename registers.

8145887, Mar 27, 2012

Jun 15, 2007

11/763760

Hung Q. Le - Austin TX, US
Dung Q. Nguyen - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 15/00, G06F 9/30, G06F 9/40, G06F 7/38, G06F 9/00, G06F 9/44

712229, 712207, 712220

A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency miss, the processing unit enters a load lookahead mode. Responsive to entering the load lookahead mode, the processing unit dispatches each instruction from a first set of instructions from a first buffer with an associated vector. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to completed execution of the first set of instructions from the first buffer, the processing unit copies the set of vectors from a first vector array to a second vector array. Then the processing unit dispatches a second set of instructions from a second buffer with an associated vector from the second vector array.

2007026, Nov 8, 2007

May 4, 2006

11/381629

Alaa Yousif - Pflugerville TX, US
Dung Nguyen - Austin TX, US
Peter Perschbach - Georgetown TX, US

DELL PRODUCTS L.P. - Round Rock TX

G06F 17/30

707010000

A remote management card is associated with a server and connected to a Network File System (NFS) server storing files. The remote management card is configured to locate a file or image on a network. The associated server my then access the files on the NFS server, facilitating the installation of an operating system or accessing another desired file.

8521998, Aug 27, 2013

Jun 4, 2010

12/793718

Christopher Michael Abernathy - Austin TX, US
Hung Qui Le - Austin TX, US
Dung Quoc Nguyen - Austin TX, US
Benjamin Walter Stolt - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/30

712235

A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.

6311267, Oct 30, 2001

Nov 20, 1998

9/196908

Dung Quoc Nguyen - Austin TX
Hung Qui Le - Austin TX

International Business Machines Corporation - Armonk NY

G06F 938

712217

A target register of an instruction is assigned a rename register in response to the instruction being issued. That is, the target register is renamed at issue time, not at dispatch time. To handle a new deadlock issue this gives rise to, rename register allocation/deallocation logic, according to the present invention, includes logic for allocating and deallocating two sets of rename registers, one set from a regular rename buffer and another set from an overflow rename buffer. According to this allocation/deallocation logic, if the oldest dispatched, noncompleted instruction is ready for assignment of a rename register and the regular rename buffer is full, then a rename register is assigned from the overflow rename buffer to this instruction.

2012021, Aug 23, 2012

Feb 23, 2011

13/032737

Christopher M. Abernathy - Austin TX, US
Mary D. Brown - Austin TX, US
Susan E. Eisen - Round Rock TX, US
James A. Kahle - Austin TX, US
Hung Q. Le - Austin TX, US
Dung Q. Nguyen - Austin TX, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G06F 12/02

711165, 711E12002

Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.