DR. DOUGLAS LEE, D.D.S.
Dentist at Pacific Ave, San Francisco, CA

5434993, Jul 18, 1995

Nov 9, 1992

7/973309

Bjorn Liencres - Palo Alto CA
Douglas Lee - San Francisco CA
Pradeep S. Sindhu - Mountain View CA
Tung Pham - San Jose CA

Sun Microsystems, Inc. - Mountain View CA
Xerox Corporation - Stamford CT

G06F 1208

395425

A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller. When the cache control system receives the new cache line information from the memory bus, it immediately replaces the cache line and allows the processing to continue.