DONATO M FORLENZA
Pharmacy in East Fishkill, NY
License number
New Jersey 28RI03557900
Issued Date
May 29, 2013
Expiration Date
Apr 30, 2017
Category
Pharmacy
Type
Pharmacist
Address
Address
East Fishkill, NY
Professional information
Functional Pattern Logic Diagnostic Method
US Patent:
7574644, Aug 11, 2009
Filed:
Jun 25, 2005
Appl. No.:
11/166019
Inventors:
Donato Forlenza - Hopewell Junction NY, US
Franco Molika - Hopewell Junction NY, US
Phillip J. Nigh - Williston VT, US
Franco Molika - Hopewell Junction NY, US
Phillip J. Nigh - Williston VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714736, 714 21, 714 25, 714 37, 714 45, 714 48, 714723, 714724, 714726, 714727, 714729, 714732, 714735, 714738, 714742
Abstract:
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
Method, Apparatus, And Computer Program Product For Diagnosing A Scan Chain Failure Employing Fuses Coupled To The Scan Chain
US Patent:
7395470, Jul 1, 2008
Filed:
Jun 9, 2005
Appl. No.:
11/149483
Inventors:
Todd M. Burdine - Zanesville OH, US
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
William J. Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
William J. Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714726
Abstract:
A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.
Implementing Diagnosis Of Transitional Scan Chain Defects Using Logic Built In Self Test Lbist Test Patterns
US Patent:
8086924, Dec 27, 2011
Filed:
Oct 13, 2008
Appl. No.:
12/250085
Inventors:
Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
Phong T Tran - Highland NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
Phong T Tran - Highland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/3177, G01R 31/40
US Classification:
714731, 714733
Abstract:
A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
Implementing Isolation Of Vlsi Scan Chain Using Abist Test Patterns
US Patent:
8065575, Nov 22, 2011
Filed:
Oct 13, 2008
Appl. No.:
12/250103
Inventors:
Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
Phong T Tran - Highland NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
Phong T Tran - Highland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714726, 714736
Abstract:
A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
Method, Apparatus, And Computer Program Product For Diagnosing A Scan Chain Failure Employing Fuses Coupled To The Scan Chain
US Patent:
7392449, Jun 24, 2008
Filed:
Dec 14, 2007
Appl. No.:
11/956480
Inventors:
Todd M. Burdine - Zainesville OH, US
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
William J. Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
William J. Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714726
Abstract:
A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.
Method And Apparatus For Performing Logic Built-In Self-Testing Of An Integrated Circuit
US Patent:
7934134, Apr 26, 2011
Filed:
Jun 5, 2008
Appl. No.:
12/133830
Inventors:
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
Bryan J. Robbins - Beavercreek OH, US
Phong T. Tran - Highland NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
Bryan J. Robbins - Beavercreek OH, US
Phong T. Tran - Highland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714733, 714726, 714727, 714729, 714734
Abstract:
A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
Ac Scan Diagnostic Method And Apparatus Utilizing Functional Architecture Verification Patterns
US Patent:
2009021, Aug 20, 2009
Filed:
Feb 15, 2008
Appl. No.:
12/031930
Inventors:
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
Phong T. Tran - Highland NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
Phong T. Tran - Highland NY, US
International Classification:
G06F 11/25, G06F 11/27, G06F 11/263
US Classification:
714729, 714733, 714738, 714E11155, 714E11169, 714E11177
Abstract:
A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST).
Implementing Deterministic Based Broken Scan Chain Diagnostics
US Patent:
7475308, Jan 6, 2009
Filed:
Apr 11, 2008
Appl. No.:
12/101925
Inventors:
Adrian C. Anderson - Lagrangeville NY, US
Todd Michael Burdine - Wappingers Falls NY, US
Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
William James Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Todd Michael Burdine - Wappingers Falls NY, US
Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
William James Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714726, 714738
Abstract:
A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.
Static And Dynamic Learning Test Generation Method
US Patent:
2007026, Nov 8, 2007
Filed:
Apr 13, 2006
Appl. No.:
11/279609
Inventors:
Donato Forlenza - Hopewell Junction NY, US
Orazio Forlenza - Hopewell Junction NY, US
Mary Kusko - Hopewell Junction NY, US
Orazio Forlenza - Hopewell Junction NY, US
Mary Kusko - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714033000
Abstract:
Exemplary embodiments include a static and dynamic test generation and simulation method including: analyzing a logic model; identifying a logic structure in the logic model whose input/output signal can be assigned to a particular logical value and remain fixed during a fault simulation test; and running the fault simulation test to check the logic model for faults.
Method For Implementing Deterministic Based Broken Scan Chain Diagnostics
US Patent:
7395469, Jul 1, 2008
Filed:
Apr 8, 2004
Appl. No.:
10/821160
Inventors:
Adrian C. Anderson - Lagrangeville NY, US
Todd Michael Burdine - Wappingers Falls NY, US
Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
William James Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Todd Michael Burdine - Wappingers Falls NY, US
Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
William James Hurley - Poughkeepsie NY, US
Phong T. Tran - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714726, 714738
Abstract:
A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.