DR. DONALD THOMAS MOORE, PH.D.
Psychologist at Robertson Blvd, Los Angeles, CA

4551814, Nov 5, 1985

Dec 12, 1983

6/560109

Donald W. Moore - Los Angeles CA
Rick A. Verstraete - Los Angeles CA

Aerojet-General Corporation - La Jolla CA

H03K 19003

364716

A logic gate structure having functionally redundant architecture for enhanced production yields and reliability comprises a plurality of two-input nodes at least some of which may be programmed by control states for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for use in adaptable problem solving machines such as robots and pattern recognition apparatus. A number of embodiments are disclosed including three and four input variable networks. Some such embodiments include selected architectural simplifications wherein certain nodes in a network are either logically fixed or entirely omitted to reduce the number of control lines.

4542508, Sep 17, 1985

Nov 21, 1983

6/553571

Donald W. Moore - Los Angeles CA

Aerojet-General Corporation - La Jolla CA

G01R 3128

371 29

A multiple input logic gate that is amenable to full testability without the "buried logic" problem of conventional VLSI logic devices and a novel dynamic test method for increasing fault-free production and simplified analysis of sub-chip faults. In one disclosed illustrative embodiment of the logic gate of the invention, the device comprises a replicated, hierarchial arranged group of six two-variable input gates to form a three-variable input gate and two such three input gates and associated logic control structure are provided on a single VLSI integrated circuit chip. Each two-variable input gate is controlled by its own programmed logic array thereby providing a selection of any of the possible 256 Boolean functions for each of the three-variable input gates on a chip. A highly advantageous dynamic test method exploits the regular hierarchial architecture of the inventive logic gate to provide top-down evaluation of each two-variable input gate until the six-gate structure is fully tested. The test method is implemented by clocking the two-variable input gates through their respective sixteen Boolean function sequentially and displaying a video map of gate output signals which will conform to a specified pattern when the device is fault-free.

4551815, Nov 5, 1985

Mar 15, 1984

6/589943

Donald W. Moore - Los Angeles CA
Rick A. Verstraete - Los Angeles CA

Aerojet-General Corporation - La Jolla CA

H03K 19003

364716

A programmable gate structure having functionally redundant architecture for enhanced production yields and reliability comprises a plurality of two-input nodes at least some of which may be programmed by control states for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for reprogramming in response to detected faults to achieve a desired gate function. A number of embodiments are disclosed including selected architectural simplifications wherein certain nodes in a network are logically fixed to reduce the number of control lines. Illustrative computer programs for generating the proper control line signals for a selected gate function in such embodiments are disclosed.

3936686, Feb 3, 1976

May 7, 1973

5/357823

Donald W. Moore - Los Angeles CA

H01J 6152, H01K 158

313 36

A cooling assembly particularly suitable for use with high brightness light sources requiring compact housing. The assembly comprises an air cooled heat sink and a connecting means being flexible and having a high thermal conductivity coefficient. This device provides an efficient method for cooling filament leads in the seal end of high brightness lamps and the joint between the lamp and reflector, thereby increasing lamp life.