Inventors:
Donald J. Pavinski - West Pittston PA, US
August Spannagel - San Francisco CA, US
Charles H. Joyner - Sunnyvale CA, US
Peter W. Evans - Mountain House CA, US
Matthew Fisher - Mountain View CA, US
Mark J. Missey - San Jose CA, US
International Classification:
H05K 7/00
Abstract:
Consistent with an aspect of the present disclosure, a package is provided that has a carrier and first and second substrates provided on the carrier. Conductive traces are provided on the first substrate (upper traces) and below it (lower traces) to provide two levels of electrical connectivity to a photonic integrated circuit (PIC) provided on the second substrate. As a result, an increased number of connections can be made to the PIC in a relatively small package, while maintaining adequate spacing and line widths for each trace. In addition, the lower traces are connected to bonding pads on the surface of the first substrate and are thus provided in the same plane as the upper traces. Testing of and access to both upper and lower traces is thus simplified.