Dennis k Williams
Plumbers at Big Sky Ct, Colorado Springs, CO

5162258, Nov 10, 1992

Mar 20, 1990

7/496399

Zachary J. Lemnios - Colorado Springs CO
David G. McIntyre - Colorado Springs CO
Dennis A. Williams - Colorado Springs CO

H01L 2144

437184

A (GaAs-resident) application specific monolithic microwave integrated circuit (ASMMIC) is fabricated through the use of footprints that include a portion of the metallization through which the circuit components within the wafer are to be interconnected. The metallization is a three layers structure, the first two layers of which include strategically arranged reactance circuit components (MIM) capacitors. A first of the three metal layers is formed on a first surface of the substrate which contains a plurality of semiconductor device regions and conductive material for ohmic contact to the regions, so that portions of the first metal layer are in ohmic contact with the conductive material. The first metal layer provides the bottom plate of the MIM capacitors. A dielectric layer, which serves as the dielectric insulator of the MIM capacitors, is formed on second portions of the first metal layer.

4959705, Sep 25, 1990

Oct 17, 1988

7/258607

Zachary J. Lemnios - Colorado Springs CO
David G. McIntyre - Colorado Springs CO
Dennis A. Williams - Colorado Springs CO

Ford Microelectronics, Inc. - Colorado Springs CO

H01L 2702, H01L 2980, H01L 2978

357 51

A (GaAs-resident) application specific monolithic microwave integrated circuit (ASMMIC) is fabricated through the use of footprints that include a portion of the metallization through which the circuit components within the wafer are to be interconnected. The metallization is a three layers structure, the first two layers of which include strategically arranged reactance circuit components (MIM) capacitors. A first of the three metal layers is formed on a first surface of the substrate which contains a plurality of semiconductor device regions and conductive material for ohmic contact to the regions, so that portions of the first metal layer are in ohmic contact with the conductive material. The first metal layer provides the bottom plate of the MIM capacitors. A dielectric layer, which serves as the dielectric insulator of the MIM capacitors, is formed on second portions of the first metal layer.

4731339, Mar 15, 1988

Aug 25, 1986

6/899574

Frank J. Ryan - Agoura CA
Man-Chung F. Chang - Thousand Oaks CA
Dennis A. Williams - Colorado Springs CO
Richard P. Vahrenkamp - Camarillo CA

Rockwell International Corporation - El Segundo CA

B44C 122

437 29

A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N. sup. - layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N. sup. + region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N. sup. + region, the N. sup. + /N. sup. - interface, and the exposed portion of the N. sup. - layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N. sup. - layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.