DR. DENNIS D. CHEN, MD
Student, Health Care in Ann Arbor, MI
License number
Michigan 4301100594
Category
Osteopathic Medicine
Type
Internal Medicine
License number
Michigan 4301100594
Category
Student, Health Care
Type
Student in an Organized Health Care Education/Training Program
Address
Address
1500 Floor Taubman Ctr, Ann Arbor, MI 48109
Phone
(734) 936-5582
(734) 936-2047
(734) 936-2047
Personal information
See more information about DENNIS D. CHEN at radaris.comName
Address
Phone
3032 Cloverly Ln, Ann Arbor, MI 48108
1846 Wyngate Dr, Troy, MI 48098
2155 Curran Dr, Troy, MI 48098
2010 Hartshorn Ave, Troy, MI 48083
Professional information
See more information about DENNIS D. CHEN at trustoria.com
Memory Cell Structure, A Memory Device Employing Such A Memory Cell Structure, And An Integrated Circuit Having Such A Memory Device
Memory Cell Structure, A Memory Device Employing Such A Memory Cell Structure, And An Integrated Circuit Having Such A Memory Device
US Patent:
8107290, Jan 31, 2012
Filed:
Apr 1, 2008
Appl. No.:
12/078547
Inventors:
Michael John Wieckowski - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Dennis Michael Chen Sylvester - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Dennis Michael Chen Sylvester - Ann Arbor MI, US
Assignee:
The Regents of the University of Michigan - The Ann Arbor MI
International Classification:
G11C 11/34, G11C 16/04
US Classification:
3651851, 36518526, 36518515
Abstract:
A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.