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Spectral And Information Theoretic Method Of Test Point, Partial-Scan, And Full-Scan Flip-Flop Insertion To Improve Integrated Circuit Testability
Spectral And Information Theoretic Method Of Test Point, Partial-Scan, And Full-Scan Flip-Flop Insertion To Improve Integrated Circuit Testability
US Patent:
8164345, Apr 24, 2012
Filed:
May 18, 2009
Appl. No.:
12/454476
Inventors:
Michael L. Bushnell - Princeton Junction NJ, US
Omar Khan - San Diego CA, US
Deepak Mehta - Martinsville NJ, US
Xinghao Chen - Endwell NY, US
Omar Khan - San Diego CA, US
Deepak Mehta - Martinsville NJ, US
Xinghao Chen - Endwell NY, US
Assignee:
Rutgers, The State University of New Jersey - New Brunswick NJ
International Classification:
G01R 31/02, G01R 31/28, G06F 17/50
US Classification:
324537, 714724, 714726, 716111, 716113
Abstract:
Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT).