Inventors:
Declan Caulfield - Encinitas CA, US
International Classification:
H04J 1/16, H04J 3/16, H04J 3/12, H04L 1/18
US Classification:
370469000, 370522000, 370252000, 714748000
Abstract:
A data packet processing system for processing data at a network interface using field programmable gate arrays (FPGAs) allows processing of data packets with lower processing delays. The data packet processing system immediately applies a plurality of processes to an incoming data packet in a concurrent manner so as to generate an action or a response packet based on the content of the incoming data packet in an efficient manner. The data packet processing system may be used to process data packets communicated between any levels of communication protocol stacks, including higher levels of such communication protocol stacks, in a manner so that the delays corresponding to multiple levels of data packet encapsulation, decapsulation, data processing and data validity testing are minimized.