DAVID WILLIAM BROWN
Pilots at Frst Brk, Sugar Land, TX

6208570, Mar 27, 2001

Aug 12, 1999

9/373487

Brian L. Brown - Sugar Land TX
David R. Brown - Sugar Land TX

Texas Instruments Incorporated - Dallas TX

G11C7/00

365201

A semiconductor memory (300) device having a redundancy test scheme is disclosed. A memory cell array (310) includes a normal section (312) and a redundant section (314, 316, and 318) of memory cells. In a normal mode of operation, the redundant section is selected if an applied address (ADD) corresponds to a defective bit in the normal section. In a redundant test mode of operation, the redundant section is selected based on a redundant test address (DFTRA, DFTCA). If the redundant test address is in the normal select logic level, a normal decode section (306 and 324) is selected. The redundant test address and a redundant test activation signal are applied to a redundant decoder (500). If the redundant test address is in a redundant select logic level and the redundant test activation signal is active, the redundant decoder is selectable based on the applied address value.

5946245, Aug 31, 1999

Nov 26, 1997

8/980098

David R. Brown - Sugar Land TX
Shoji Wada - Tokyo, JP

Texas Instruments Incorporated - Dallas TX

G11C 700

365201

A circuit for testing a memory cell array 100. The circuit includes a test circuit 104 coupled to the array and includes a data output line 106 and a failure signal output line 108. A shift register 110, which includes a plurality of latches, a clock signal input 114, and an output line 116, is connected to the failure signal output line of the test circuit. The circuit also includes a three-state output buffer driver 118, the buffer driver including a data input line, a failure signal input line, and a data output line. The failure signal line of the buffer driver is connected to the output line of the shift register 110. Upon detecting a defective memory cell in the array, the test circuit produces a failure signal on the failure signal output line 116 of the test circuit. The failure signal is then sent to the shift register 110 causing the buffer driver 118 to enter a high-impedance state in response to said failure signal. The shift register 110 comprises a number of latches in accordance with the desired latency variability of the system or test equipment using the test circuit.

5831925, Nov 3, 1998

Dec 2, 1997

8/982672

David R. Brown - Sugar Land TX
Shoji Wada - Tokyo, JP
Kazuya Ito - Hamura, JP
Yasuhito Ichimura - Ibaraki, JP
Ken Saitoh - Akishima, JP

Texas Instruments Incorporated - Dallas TX

G11C 800, G11C 700

36523003

A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality.

2002017, Nov 21, 2002

Apr 10, 2001

09/832070

David Brown - Sugar Land TX, US
Richard Robertson - Baton Rouge LA, US

C07C002/02

585/502000, 585/520000, 585/525000

A process for the oligomerization of ethylene to a mixture of olefinic products having high linearity is provided, by using a catalyst comprising a reaction product of a simple divalent nickel salt; a boron hydride reducing agent; a water soluble base; a ligand selected from an o-dihydrocarbylphosphinobenzoic acid and alkali metal salt thereof; and, a phosphite.

6310506, Oct 30, 2001

Oct 10, 1997

8/948900

David R. Brown - Sugar Land TX

Texas Instruments Incorporated - Dallas TX

H03H 1126

327284

A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.

5377144, Dec 27, 1994

Jul 27, 1993

8/097820

David R. Brown - Sugar Land TX

Texas Instruments Inc. - Dallas TX

G11C 700

36518902

A memory part (10), with memory (14) subarrays arranged in different ways, provides one data input and output path for normal operation and another data input and output path for test mode operation. The part furnishes one data output multiplexer (40) connected between the memory (14) subarrays and the data output buffers (24) for normal operation. The part furnishes another data output multiplexer (52) connected between the memory (14) subarrays and the data output buffers for test mode operation. Test mode circuits (30) on the memory part select operation of the one and the other multiplexer. Data input gating circuits connect between the data in buffers (22) and the memory (14) subarrays and connect all or one of the data input leads D0-8 to the memory subarrays in response to operation of the test mode circuits.

2004011, Jun 17, 2004

Dec 11, 2002

10/316812

Howard Fong - Sugar Land TX, US
Michael Potter - Sugar Land TX, US
David Brown - Sugar Land TX, US

C07C006/02

585/643000, 585/644000, 585/324000

Ring opening cross metathesis of secondary non-cyclic hydrocarbons with cyclic unsaturated hydrocarbons having 8 carbon atoms or more to produce corresponding unsaturated product hydrocarbons having more than 8 carbon atoms.

6005430, Dec 21, 1999

Feb 25, 1998

9/030148

Brian L. Brown - Sugar Land TX
David R. Brown - Sugar Land TX

Texas Instruments Incorporated - Dallas TX

H03H 1126

327277

A clock circuit including a first delay circuit comprising an input terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals. The input terminal is coupled to the first input terminal of a first logic circuit in the series and the output of the first logic circuit is coupled to the second input terminal of a second logic circuit in the series. The output of the second logic circuit is coupled to the first input terminal of a third logic circuit in the series, and subsequent logic circuits in the series have alternately the first or second input terminal coupled to the output terminal of an immediately preceding logic circuit in the series. The circuit also includes a second delay circuit comprising an output terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals. The output terminal of the first logic circuit in the series is coupled to the second input terminal of a second logic circuit in the series.