DAVID WHITE
Psychologist in Cambridge, MA
License number
Massachusetts 3355
Issued Date
Dec 2, 1983
Expiration Date
Jun 30, 2018
Type
Psychologist
Address
Address
Cambridge, MA 02139
Organization information
See more information about DAVID WHITE at bizstanding.comDavid White
955 Massachusetts Ave, Cambridge, MA 02139
Industry:
Nonclassifiable Establishments
Professional information
David White, Cambridge MA - Lawyer
Address:
55 Cambridge Pkwy, Cambridge, MA 02142
Experience:
47 years
Specialties:
Antitrust, Business Law, Intellectual Property, Real Estate Law
Jurisdiction:
Massachusetts (1979)
Memberships:
Massachusetts State Bar (1979)
David A. White, Cambridge MA - Lawyer
Office:
55 Cambridge Pkwy, Cambridge, MA
ISLN:
902808209
Admitted:
1974
University:
Northeastern University, B.S.L.A.
Law School:
Boston College, J.D.
Characterization And Verification For Integrated Circuit Designs
US Patent:
7712056, May 4, 2010
Filed:
Feb 6, 2007
Appl. No.:
11/703399
Inventors:
David White - Cambridge MA, US
Taber H. Smith - San Jose CA, US
Taber H. Smith - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50, G06F 19/00, G21K 5/00, G03F 1/00
US Classification:
716 4, 716 21, 700121, 700120, 378 35, 430 5
Abstract:
Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
Characterization And Verification For Integrated Circuit Designs
US Patent:
7174520, Feb 6, 2007
Filed:
Dec 17, 2002
Appl. No.:
10/321283
Inventors:
David White - Cambridge MA, US
Taber H. Smith - Fremont CA, US
Taber H. Smith - Fremont CA, US
Assignee:
Praesagus, Inc. - Cambridge MA
International Classification:
G06F 17/50, G06F 19/00, G03F 1/00, G21K 5/00
US Classification:
716 4, 716 21, 700110, 700120, 700121, 430 5, 378 35
Abstract:
Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
Test Masks For Lithographic And Etch Processes
US Patent:
7062730, Jun 13, 2006
Filed:
Dec 17, 2002
Appl. No.:
10/321281
Inventors:
David White - Cambridge MA, US
Taber H. Smith - San Jose CA, US
Taber H. Smith - San Jose CA, US
Assignee:
Praesagus, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 19
Abstract:
A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
Dummy Fill For Integrated Circuits
US Patent:
7363598, Apr 22, 2008
Filed:
Sep 22, 2004
Appl. No.:
10/947500
Inventors:
Taber H. Smith - Fremont CA, US
Vikas Mehrotra - Fremont CA, US
David White - Cambridge MA, US
Vikas Mehrotra - Fremont CA, US
David White - Cambridge MA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 4, 716 10, 716 11
Abstract:
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Test Masks For Lithographic And Etch Processes
US Patent:
7243316, Jul 10, 2007
Filed:
Dec 17, 2002
Appl. No.:
10/321281
Inventors:
David White - Cambridge MA, US
Taber H. Smith - San Jose CA, US
Taber H. Smith - San Jose CA, US
Assignee:
Praesagus, Inc. - Cambridge MA
International Classification:
G06F 17/50, G06F 19/00
US Classification:
716 4, 716 19, 700121, 702 97
Abstract:
A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
Dummy Fill For Integrated Circuits
US Patent:
7356783, Apr 8, 2008
Filed:
Sep 22, 2004
Appl. No.:
10/947195
Inventors:
Taber H. Smith - Fremont CA, US
Vikas Mehrotra - Fremont CA, US
David White - Cambridge MA, US
Vikas Mehrotra - Fremont CA, US
David White - Cambridge MA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 4, 716 10, 716 11
Abstract:
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Electronic Design For Integrated Circuits Based On Process Related Variations
US Patent:
7353475, Apr 1, 2008
Filed:
Dec 17, 2002
Appl. No.:
10/321777
Inventors:
David White - Cambridge MA, US
Taber H. Smith - San Jose CA, US
Taber H. Smith - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 5, 716 4
Abstract:
A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, and an impact is determined of the variations of feature dimensions on electrical characteristics of the integrated circuit. An impact is determined of the topological variations on electrical characteristics of the integrated circuit. An RC extraction tool is used in conjunction with the using of the model and the determining of the impact.
Dummy Fill For Integrated Circuits
US Patent:
7124386, Oct 17, 2006
Filed:
Jun 7, 2002
Appl. No.:
10/164844
Inventors:
Taber H. Smith - Fremont CA, US
Vikas Mehrotra - Fremont CA, US
David White - Cambridge MA, US
Vikas Mehrotra - Fremont CA, US
David White - Cambridge MA, US
Assignee:
Praesagus, Inc. - Cambridge MA
International Classification:
G06F 17/50
US Classification:
716 10, 716 9, 716 8
Abstract:
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.