David Wayne Reed
Electrician in Westminster, CO

6493163, Dec 10, 2002

Mar 3, 2000

09/518111

David E. Reed - Westminster CO
Trent Dudley - Littleton CO

Cirrus Logic, Inc. - Austin TX

G11B 509

360 51, 360 46

A disk drive system is disclosed that includes a disk device coupled to control circuitry. The disk device transfers a read signal representing data to the control circuitry, where the control circuitry is configured to receive the read signal and convert it into a data signal. To convert the read signal, the control circuitry samples the read signal to generate read samples. The control circuitry interpolates the read samples using phase error data to generate a first interpolated sample and a second interpolated sample. To generate the phase error data, the control circuitry subtracts the second interpolated sample from the first interpolated sample to generate a first result. The control circuitry subtracts the first interpolated sample from the second interpolated sample to generate a second result. The control circuitry slices the second result to generate a third result. The control circuitry then multiplies the first result and the third result to generate the phase error data.

6490110, Dec 3, 2002

Dec 19, 2000

09/740748

David E. Reed - Westminster CO
Stephen A. Turk - Longmont CO
Li Du - Broomfield CO

Cirrus Logic, Inc. - Austin TX

G11B 509

360 48, 360 53, 360 7708

Servo circuitry is disclosed that is configured to operate with a magnetic disk drive system. The servo circuitry is comprised of a first servo detector system, a second servo detector system, and a comparator. The first servo detector system and the second servo detector system each receive samples, taken from a read signal, that include servo data. The first servo detector system compares the samples to a plurality of servo codes to generate a first selected code. The second servo detector system compares a first shifted version of the samples to the plurality of servo codes to generate a second selected code. The comparator receives the selected codes and selects one of the selected codes. The selected code represents the servo data. The servo circuitry could also include a third servo detector system that operates on a second shifted version of the samples.

6614609, Sep 2, 2003

Mar 8, 2000

09/520535

David E. Reed - Westminster CO
Sian She - Broomfield CO

Cirrus Logic, Inc. - Austin TX

G11B 509

360 51, 360 7702

A disk drive system is disclosed that includes a disk device coupled to control circuitry. The control circuitry includes a read channel with a detector that detects a bit sequence associated with Gray codes and delays indications of the bit sequence detection to handle phase shifts. The detector generates a Gray code detection signal in response to the delayed indications. The control circuitry processes the Gray code in response to the Gray code detection signal.

6594217, Jul 15, 2003

Jun 22, 1999

09/338020

David E. Reed - Westminster CO

Cirrus Logic, Inc. - Austin TX

G11B 509

369 5919, 369 4748, 341 68, 375341

A disk drive system comprises control circuitry and a disk device. The disk device transfers an analog signal representing servo data and user data from a disk device to the control circuitry. The servo data includes servo synch marks. The control circuitry processes the analog signal to generate a digital signal representing the user data. The control circuitry includes Viterbi circuitry and servo circuitry. The Viterbi circuitry interleaves and sums samples of the analog signal. The Viterbi circuitry then processes the sums using two states, an even magnet length constraint, a D=1 constraint, and a sliding threshold algorithm to generate a bit sequence. The servo circuitry processes the bit sequence to detect the servo synch marks.

6023386, Feb 8, 2000

Oct 31, 1997

8/961727

David E. Reed - Westminster CO
William G. Bliss - Thornton CO

Cirrus Logic, Inc. - Fremont CA

G11B 509

360 51

In a magnetic disk storage system, a sampled amplitude read channel is disclosed that employs a fault tolerant sync mark detector for detecting a sync mark from the channel samples in order to synchronize a time varying sequence detector. The read channel preferably employs PR4 equalization for timing recovery and gain control, and EEPR4 equalization for sequence detection. The EEPR4 sequence detector operates according to a time varying state machine matched to a predetermined trellis code constraint. Because the state machine is time varying, the data stream must be synchronized at the input of the sequence detector rather than at the output as in the prior art. The present invention provides a fault tolerant sync mark detector that detects a sync mark from the EEPR4 channel samples before being input into the sequence detector. In one embodiment, the sync mark detector accumulates a squared error between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the accumulated squared error is less than a predetermined lower threshold. In an alternative embodiment, the sync mark detector computes a correlation between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the correlation is greater than a predetermined upper threshold.

6246723, Jun 12, 2001

May 4, 1998

9/072285

William G. Bliss - Thornton CO
David E. Reed - Westminster CO
Marvin L. Vis - Longmont CO
German S. Feyh - Boulder CO

Cirrus Logic, Inc. - Austin TX

H04L 512

375265

A sampled amplitude read channel is disclosed for disc storage systems that extracts early-decisions from a discrete-time trellis sequence detector to generate estimated target values for use in decision-directed timing recovery, gain control, and adaptive equalization. The trellis sequence detector comprises a metric generator for generating error metrics corresponding to a plurality of states of a state transition diagram, and a plurality of path memories which correspond to the paths of a trellis. The path memories store a plurality of survivor sequences which eventually merge into a most likely sequence at the output of the path memories. To reduce the latency in generating the estimated target samples, the trellis sequence detector outputs an early-decision from an intermediate location within the path memories. The early-decision is then converted into the partial response signaling space of the read signal samples. To improve the accuracy in estimating the target sample values, the accumulated metrics of a predetermined number of states are compared and the early-decision value is selected from the path memory having the smallest error metric.

7884681, Feb 8, 2011

Apr 30, 2008

12/112006

Nadim Khlat - Midi-Pyrenees, FR
Ruediger Bauder - Feldkirchen-Westerham, DE
David Reed - Westminster CO, US
Baker P. Scott - Boulder CO, US

RF Micro Devices, Inc. - Greensboro NC

H03C 1/00, H03C 1/02, H03C 1/06

332149, 332159, 332160

Embodiments of the present invention include amplitude-modulated or polar-modulated radio frequency (RF) power amplifier circuitry, in which an envelope power supply input to an RF power amplifier is powered by a pre-distorted amplitude modulation (AM) power supply. The pre-distorted AM power supply receives an AM signal, which is then pre-distorted and amplified to provide an AM power supply signal to the RF power amplifier. The pre-distortion of the AM signal is used to improve the linearity, the efficiency, or both, of the RF power amplifier. The pre-distortion provides a feed-forward system, which may allow use of a reduced bandwidth pre-distorted AM signal to an AM power supply and a reduced bandwidth AM power supply, which may increase efficiency.

2002006, Jun 6, 2002

Dec 5, 2000

09/730091

David Reed - Westminster CO, US
Stephen Turk - Longmont CO, US
Li Du - Broomfield CO, US

Cirrus Logic, Inc.

G06F011/00

714/054000

Servo circuitry is disclosed that is configured to operate with a magnetic disk drive system. The servo circuitry is comprised of a first servo detector system, a second servo detector system, and a comparator. The first servo detector system and the second servo detector system each receive samples, taken from a read signal, that include servo data. The first servo detector system compares the samples to a plurality of servo codes to generate a first selected code. The second servo detector system compares a first shifted version of the samples to the plurality of servo codes to generate a second selected code. The comparator receives the selected codes and selects one of the selected codes. The selected code represents the servo data. The servo circuitry could also include a third servo detector system that operates on a second shifted version of the samples. Alternatively, the first servo detector system, the second servo detector system, and the third servo detector system could each be programmed with different servo codes. The first servo detector system compares the samples to a plurality of first servo codes. The second servo detector system compares the samples to a plurality of second servo codes. The third servo detector system compares the samples to a plurality of third servo codes. The second servo codes and the third servo codes are shifted versions of the first servo codes. In either embodiment, the servo circuitry advantageously has improved phase shift tolerance.

5802118, Sep 1, 1998

Jul 29, 1996

8/681578

William G. Bliss - Thornton CO
David E. Reed - Westminster CO
Richard T. Behrens - Louisville CO

Cirrus Logic, Inc. - Fremont CA

H04B 110

375350

A sampled amplitude read channel is disclosed for reading binary data from a computer disk storage system, wherein the read channel sub-samples an analog read signal at a rate lower than the baud rate and detects the binary data from the sub-sampled values using a sequence detector. In one embodiment, the sub-sampled values are interpolated to generate synchronous sample values which are processed by a conventional sequence detector. In another embodiment, the sequence detector is modified to detect the binary data directly from the sub-sampled values. In yet another embodiment, the sequence detector comprises a remodulator and an error pattern detector for detecting and correcting bit errors in the detected binary data. In addition, for the various embodiments a channel code increases the distance property of the sequence detector in order to compensate for the degradation in performance caused by sub-sampling.