DAVID WANG
Acupuncture at Mattos Dr, Fremont, CA

2013023, Sep 12, 2013

Dec 9, 2010

13/057115

Mehrdad M Moslehi - Los Altos CA, US
Pawan Kapur - Burlingame CA, US
Karl-Josef Kramer - San Jose CA, US
David Xuan-Qi Wang - Fremont CA, US
Sean Seutter - San Jose CA, US
Virenda V Rana - Los Gatos CA, US
Anthony Calcaterra - Milpitas CA, US
Emmanuel Van Kerschaver - Mountain View CA, US
Duncan Harwood - Santa Clara CA, US
Majid Mansoori - Richardson TX, US
Michael Wingert - Los Gatos CA, US

SOLEXEL, INC. - Milpitas CA

H01L 31/02

136256, 438 71

A back contact back junction solar cell using semiconductor wafers and methods for manufacturing are provided. The back contact back junction solar cell comprises a semiconductor wafer having a doped base region, a light capturing frontside surface, and a doped backside emitter region. A frontside and backside dielectric layer and passivation layer provide enhance light trapping and internal reflection. Backside base and emitter contacts are connected to metal interconnects forming a metallization pattern of interdigitated fingers and busbars on the backside of the solar cell.

2010014, Jun 17, 2010

Nov 13, 2009

12/618663

David Xuan-Qi Wang - Fremont CA, US
Mehrdad M. Moslehi - Los Altos CA, US

SOLEXEL, INC. - Milpitas CA

H01L 29/04, H01L 29/06, H01L 21/20

257627, 257618, 438478, 257 49, 257E29022, 257E29004, 257E2109

A three-dimensional thin-film semiconductor substrate having a plurality of ridges on the surface of the semiconductor substrate which define a base opening of an inverted pyramidal cavity and walls defining the inverted pyramidal cavity is provided. And a fabrication method for a 3-D TFSS by forming a porous silicon layer on a silicon template having a top surface aligned along a (100) crystallographic orientation plane of the silicon template and a plurality of walls each aligned along a (111) crystallographic orientation plane of the silicon template and forming an inverted pyramidal cavity. The porous silicon layer forms substantially conformal on the silicon template. Then forming a substantially conformal epitaxial silicon layer on the porous silicon layer and releasing the epitaxial silicon layer from the silicon template.

7058218, Jun 6, 2006

Sep 28, 1998

09/162244

Robert A. Drebin - Palo Alto CA, US
David Wang - Fremont CA, US
Christopher J. Migdal - Mountain View CA, US

Silicon Graphics, Inc. - Mountain View CA

G06K 9/00

382167, 382166, 358539

The present invention provides for a method of and apparatus for compressing and uncompressing image data. According to one embodiment of the present invention, the method of compressing a color cell comprises the steps of: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color. In one embodiment, the color cell includes a matrix of 4x4 pixels, the bitmask includes 32-bits and each of the color values includes 16-bits such that a compression rate of 4-bits per pixel is achieved. The present invention is particularly applicable to compress texture data such that the texture data can be more efficiently cached and moved during texture mapping.

2013014, Jun 6, 2013

Dec 30, 2010

13/520139

Mehrdad M. Moslehi - Los Altos CA, US
David Xuan-Qi Wang - Fremont CA, US

Solexel, Inc. - Milpitas CA

H01L 21/683, H01L 21/762, H01L 21/768

361234, 438675, 438455

In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode regions separated by a frontside trench through the top semiconductor layer at least to an underlying insulating layer positioned between the top semiconductor layer and a bottom semiconductor layer. A dielectric layer covers the top exposed surfaces of the carrier. Backside trenches through the bottom semiconductor layer at least to the insulating layer form isolated backside regions corresponding to the frontside positive and negative electrode regions. Backside contacts positioned on the bottom semiconductor layer and coupled to the positive and negative electrode regions allow for the electric charging of the frontside electrode regions.

2012017, Jul 12, 2012

Jan 9, 2012

13/345935

David Xuan-Qi Wang - Fremont CA, US
Mehrdad M. Moslehi - Los Altos CA, US

SOLEXEL, INC. - Milpitas CA

C30B 11/00, B44C 1/22

117223, 216 2

A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.

7190460, Mar 13, 2007

Oct 28, 2003

10/695007

David Y. Wang - Fremont CA, US

Therma-Wave, Inc. - Fremont CA

G01N 21/47

356446, 3562375

A system for focusing broadband light within a reflectometer includes a concave spherical mirror for gathering light from the surface of a sample under inspection. The concave spherical mirror projects the received light to a convex spherical mirror. The combination of the two mirrors captures the light diverging from the sample and collimates the light into parallel rays. The light can then be passed through an aperture prior to entering a detector. Each of the two mirrors is fabricated as an off-axis section of a spherical mirror and positioned to form a partial Schwarzschild design without the associated problem of a central obscuration.

8294026, Oct 23, 2012

Nov 13, 2009

12/618668

David Xuan-Qi Wang - Fremont CA, US
Mehrdad M. Moslehi - Los Altos CA, US

Solexel, Inc. - Milpitas CA

H01L 31/00, H01L 21/00

136256, 438 71

A three-dimensional solar cell comprising a semiconductor substrate with an inverted pyramidal cavity, emitter metallization regions on ridges on the surface of the semiconductor substrate which define an opening of the inverted pyramidal cavity, and base metallization regions on a region which form the apex of the inverted pyramidal cavity. A method for fabricating a three-dimensional thin-film solar cell from an inverted pyramidal three-dimensional thin-film silicon substrate by doping ridges on the surface of the semiconductor substrate which define an opening of an inverted pyramidal cavity on the substrate to form an emitter region, and doping a region which forms the apex of the inverted pyramidal cavity to form a base region. Adding a surface passivation layer to the surface of the substrate. Selectively etching the passivation layer from the emitter region and base region.

2013014, Jun 6, 2013

Dec 15, 2010

13/515848

David Xuan-Qi Wang - Fremont CA, US
Mehrdad Moslehi - Los Altos CA, US

SOLEXEL, INC. - Milpitas CA

H01L 21/677

294188

This disclosure presents mobile vacuum carriers that may be used to support thin substrates that would otherwise be too brittle to transport and process. This disclosure relates to the processing of thin semiconductor substrates and has particular applicability to the fields of photovoltaic solar cells, semiconductor microelectronic integrated circuits, micro-electro-mechanical systems (MEMS), optoelectronic devices (such as light-emitting diodes, lasers, photo detectors), data storage devices, etc.