DAVID W MEYER
Nursing at Harvard Ave, Denver, CO

5949781, Sep 7, 1999

Jun 6, 1995

8/467311

Bradford C. Lincoln - Boulder CO
Douglas M. Brady - Boulder CO
David R. Meyer - Lakewood CO
Warner B. Andrews - Boulder CO

Brooktree Corporation - San Diego CA

H04L 1256

370395

A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i. e. terminals) are scheduled at table positions dependent upon their individual transfer rates.

6075790, Jun 13, 2000

Dec 11, 1996

8/764692

Bradford C. Lincoln - Boulder CO
David R. Meyer - Lakewood CO

Brooktree Corporation - San Diego CA

H04L 1228

370398

A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

7009981, Mar 7, 2006

Nov 4, 1999

09/433850

Bradford C. Lincoln - Boulder CO, US
David R. Meyer - Lakewood CO, US

Mindspeed Technologies, Inc. - Newport Beach CA

H04L 12/28

370398, 370412

A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

6185223, Feb 6, 2001

Dec 4, 1996

8/767109

David R. Meyer - Lakewood CO
Warner B. Andrews - Boulder CO

Conexant Systems, Inc. - Newport Beach CA

H04L 1254, H04L 1228, H04L 1256, H04L 1266

370429

An edge device for an ATM system includes a fire wall protection which proactively limits the number of cells per connection provided to the devices connected to the edge device. The edge device may be connected to ethernets, LANs, frame relay networks, communication equipment, work stations, or various other computer and communication equipment. The edge device preferably includes a counter for each connection associated with the ATM system. The counter is decremented each time a memory location in the host memory is utilized and incremented whenever the memory location is relieved of storing the data cell. An SAR unit operates to proactively prevent congestion by limiting each connection to a particular number of storage elements.

2012019, Aug 2, 2012

Dec 8, 2011

13/314787

Anand P. Narayan - Bangalore, IN
Greg Graham - Boulder CO, US
David R. Meyer - Lakewood CO, US
Prashant Jain - Westminster CO, US

RAMBUS INC. - Sunnyvale CA

H04B 15/00, H04L 27/01

375232, 375346

An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

8085889, Dec 27, 2011

Sep 19, 2007

11/858074

Anand P Narayan - Boulder CO, US
Greg Graham - Boulder CO, US
David R Meyer - Lakewood CO, US
Prashant Jain - Westminster CO, US

Rambus Inc. - Sunnyvale CA

H03D 1/04

375346

An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.