MR. DAVID W CHAN, DDS
Dentist in San Jose, CA

License number
California 33027
Category
Dentist
Type
General Practice
Address
Address
1095 Branham Ln. Suite #101, San Jose, CA 95136
Phone
(408) 978-8888

Organization information

See more information about DAVID W CHAN at bizstanding.com

Lee Dental Group - David W Chan DDS

1095 Branham Ln STE 101, San Jose, CA 95136

Categories:
Dentists
Phone:
(408) 978-8888 (Phone)

Professional information

David Chan Photo 1

System And Network Convergence Engineer

Position:
IVR Software Support Engineer at Convergys
Location:
San Francisco Bay Area
Industry:
Computer Networking
Work:
Convergys - Mountain View, CA since Dec 2005 - IVR Software Support Engineer any bay area companies - Any locations if there is any golden opportunities Sep 2011 - Dec 2011 - Seeking technical job opportunities to contribute my talents Edify Corp/Everyone.net (Contractor Pos.) - San Jose, CA Oct 2003 - Dec 2005 - IT Technical Consultant, Designing and Developing of the Help Desk System Fairchild Semiconductor - San Jose, CA May 1997 - Oct 2003 - IT Technical Lead Engineer, Infrastructure Engineering and Implementation
Education:
Southern Illinois University, Carbondale
BS, Electrical Engineering, concentrating in Digital Design, and Minor in Mathematics.
Skills:
Network Administration, Telecommunications
Interests:
Know people, explore new ideas, ping pong, tennis


David Chan Photo 2

David Chan - San Jose, CA

Work:
Securitas Security Services
Security Officer
AutoNation Acura of Stevens Creek - Santa Clara, CA
Assistant Service Manager
South Bay Honda - Milpitas, CA
Service Advisor (Bilingual)
KBT Communications - Sunnyvale, CA
Regional Sales Executive
AT&T Mobility - Cerritos, CA
Small Business Account Manager
Placement Pros - San Francisco, CA
Junior Security Placement Coordinator
Education:
California State Polytechnic University - Pomona, CA
B.A. in Art
Skills:
Professionally trained on how to deal with customers and how to complete a complicated sale. I attended a trade school training and sales training in order to be able to sell on the showroom floor. I can also speak fluent Cantonese, Mandarin, and some Spanish. I have knowledge in using both a PC and MAC computer. I am proficient in Microsoft Word, Excel, Windows, PowerPoint, Goldmine, TKO Tiny Term, In-Time, Adobe Photoshop, Illustrator, Quark Express, Adobe Premier, and Dream Weaver.


David Chan Photo 3

David Chan - San Jose, CA

Work:
Adobe Systems
SaaS Applications Systems Engineer
Agate Logic - Cupertino, CA
System Administrator
Technorati Inc - San Francisco, CA
System Administrator
Sun Microsystems - Menlo Park, CA
System Administrator
Chromax Golf Company - Boulder, CO
Network and Server Consultant/Offsite Sales Associate
Sun Microsystems - Menlo Park, CA
Release Engineer
Network Associates - Santa Clara, CA
Release Engineer
Education:
University of Phoenix - San Jose, CA
Bachelor of Science in Information Technology


David Chan Photo 4

David Chan

Work:
Top Microsystems
Account Manager
Intermak USA - San Jose, CA
Inside Sales Representative
Hunter Laboratories - Campbell, CA
Client Service Representative
Adonis Furniture - Milpitas, CA
B2B Inside Sales Representative
Education:
College of Management - Pleasanton, CA
Certificate of Completion
James Lick High School - San Jose, CA
Diploma
San Jose City College - San Jose, CA
Associates of Arts


David Chan Photo 5

David Chan - San Jose, CA

Work:
South Bay Honda - Milpitas, CA
Service Advisor (Bilingual)
KBT Communications - Sunnyvale, CA
Regional Sales Executive
AT&T Mobility - Cerritos, CA
Small Business Account Manager
Placement Pros - San Francisco, CA
Junior Security Placement Coordinator
GMR Marketing - New Berlin, WI
Product Marketing Specialist / Coordinator / Field Supervisor
Education:
California State Polytechnic University - Pomona, CA
B.A. in Art


David Chan Photo 6

David Chan - San Jose, CA

Work:
Quanta Computer - Fremont, CA
Assembly Line Worker
Education:
independance high - San Jose, CA
High School Diploma


David Chan Photo 7

Thin Film Cmos Calibration Standard Having Protective Cover Layer

US Patent:
6830943, Dec 14, 2004
Filed:
Nov 4, 2003
Appl. No.:
10/702165
Inventors:
Wai Lo - Lake Oswego OR
David Chan - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2166
US Classification:
438 18, 438 17, 438 14, 438778
Abstract:
Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.


David Chan Photo 8

Composite Semiconductor Gate Dielectrics

US Patent:
6087229, Jul 11, 2000
Filed:
Mar 9, 1998
Appl. No.:
9/037588
Inventors:
Sheldon Aronowitz - San Jose CA
David Chan - San Jose CA
James Kimball - San Jose CA
David Lee - San Jose CA
John Haywood - Santa Clara CA
Valeriy Sukharev - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 21336
US Classification:
438287
Abstract:
Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.


David Chan Photo 9

Method Of Forming Variable Thickness Gate Dielectrics

US Patent:
6033998, Mar 7, 2000
Filed:
Mar 9, 1998
Appl. No.:
9/038684
Inventors:
Sheldon Aronowitz - San Jose CA
David Chan - San Jose CA
James Kimball - San Jose CA
David Lee - San Jose CA
John Haywood - Santa Clara CA
Valeriy Sukharev - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2176
US Classification:
438786
Abstract:
Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.


David Chan Photo 10

Multi-Way Polling, Branching And Waiting Opcode

US Patent:
4868469, Sep 19, 1989
Filed:
May 16, 1988
Appl. No.:
7/194608
Inventors:
David A. Chan - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G05B 1918
US Classification:
318254
Abstract:
Disclosed are an opcode and associated circuitry which enable various polling, branching and waiting logic to occur within one machine cycle. This circuitry can be applied in a variety of different applications where multi-way branching is required promptly when particular input patterns or desired state signals are detected.