MR. DAVID W CHAN, DDS
Dentist in San Jose, CA

6830943, Dec 14, 2004

Nov 4, 2003

10/702165

Wai Lo - Lake Oswego OR
David Chan - San Jose CA

LSI Logic Corporation - Milpitas CA

H01L 2166

438 18, 438 17, 438 14, 438778

Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

6087229, Jul 11, 2000

Mar 9, 1998

9/037588

Sheldon Aronowitz - San Jose CA
David Chan - San Jose CA
James Kimball - San Jose CA
David Lee - San Jose CA
John Haywood - Santa Clara CA
Valeriy Sukharev - Cupertino CA

LSI Logic Corporation - Milpitas CA

H01L 21336

438287

Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.

6033998, Mar 7, 2000

Mar 9, 1998

9/038684

Sheldon Aronowitz - San Jose CA
David Chan - San Jose CA
James Kimball - San Jose CA
David Lee - San Jose CA
John Haywood - Santa Clara CA
Valeriy Sukharev - Cupertino CA

LSI Logic Corporation - Milpitas CA

H01L 2176

438786

Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.

4868469, Sep 19, 1989

May 16, 1988

7/194608

David A. Chan - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G05B 1918

318254

Disclosed are an opcode and associated circuitry which enable various polling, branching and waiting logic to occur within one machine cycle. This circuitry can be applied in a variety of different applications where multi-way branching is required promptly when particular input patterns or desired state signals are detected.