David W Blair
Psychologist in Salt Lake City, UT

5262965, Nov 16, 1993

Oct 31, 1988

7/265422

Leland K. Putnam - Salt Lake City UT
Phillip H. Lucht - Salt Lake City UT
David K. Blair - Salt Lake City UT
Scott K. Pritchett - Sandy UT

BTS-Broadcast Television Systems, Inc. - Salt Lake City UT

G06F 300

395101

A high performance computer graphics image computation system architecture is disclosed. The system architecture includes a computational processor ring which includes a plurality of closely coupled computational subsystems. The computational subsystems operate asynchronously and each is interconnected with two adjacent computational subsystems. The architecture of the processor ring allows rapid communication between the computational subsystems while avoiding a deadlock condition. The system architecture also includes a video processor ring wherein a plurality of video processors are synchronously linked together. A plurality of local communication paths couple the computational subsystems to the video processors. The video processor ring is able to move massive amounts of data, in the form of digital video signals, from various points within the system. The computational processor ring is able to rapidly carry out graphic image computation tasks and graphic image data is moved around in the system by way of the video processor ring.

5539660, Jul 23, 1996

Sep 23, 1993

8/125996

David K. Blair - Bennion UT
Scott K. Curtis - Salt Lake City UT
Philip H. Lucht - Salt Lake City UT

Philips Electronics North America Corporation - New York NY

H04Q 1100

364514C

The system includes a plurality of disk arrays for storing, sequentially, contiguous segments of a data block. In the case of movies, each segment includes, for example, a few seconds of each relevant movie. An electronic commutator sequentially connects the disk arrays to a corresponding plurality of access channels. While the individual connections between each of the disk arrays and each of the access channels have a certain bit capacity, the overall bit capacity of the system is that certain bit capacity times the number of corresponding disk arrays and access channels. The electronic commutator switches sequentially between the respective connections at a predetermined rate which is commensurate with the size of the segments stored on the disk arrays and which is dependent on the desired amount of wait time for one access channel to be connected to each of the disk arrays.

5671386, Sep 23, 1997

Feb 16, 1995

8/389672

David Kim Blair - Bennion UT
Scott Karl Curtis - Salt Lake City UT
Philip Harrison Lucht - Salt Lake City UT

Philips Electronics North America Corporation - New York NY

G06F 1200

395405

A system having N access channels, M individual disk storage arrays, a commutator for connecting each of the access channels to each of the storage arrays; and a control unit for causing the commutator to connect each of the access channels to each of the storage arrays. The disk storage arrays are capable of storing contiguous segments of a data block. In the case of movies, each segment includes, for example, a few seconds of each relevant movie. The commutator connects the access channels to the disk storage arrays in a manner whereby each of the access channels has access to all of the data. The system is such that each access channel can receive data at the maximum system bandwidth. In addition, data can be written into the storage arrays by one access channel, while another of the access channels is receiving data, both at the maximum system bandwidth. In one embodiment of the system, each of the access channels is connected to a downstream channel, in which at least two of those downstream channel have a different bandwidth than the system bandwidth.