DAVID VOLFSON
Broker in Worcester, MA
License number
Massachusetts 80240
Issued Date
Apr 1, 1986
Expiration Date
May 25, 2000
Type
Salesperson
Address
Address
Worcester, MA 01609
Professional information
High-Density, Multi-Level Interconnects, Flex Circuits, And Tape For Tab
US Patent:
4980034, Dec 25, 1990
Filed:
Apr 4, 1989
Appl. No.:
7/333179
Inventors:
David Volfson - Worcester MA
Stephen D. Senturia - Boston MA
Stephen D. Senturia - Boston MA
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
C25D 500
US Classification:
204 384
Abstract:
A multi-layer interconnect structure of alternating dielectric (e. g. , polyimide) and metal (e. g. , copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.
High-Density, Multi-Level Interconnects, Flex Circuits, And Tape For Tab
US Patent:
5106461, Apr 21, 1992
Filed:
Dec 21, 1990
Appl. No.:
7/632364
Inventors:
David Volfson - Worcester MA
Stephen D. Senturia - Boston MA
Stephen D. Senturia - Boston MA
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
C25D 500
US Classification:
205125
Abstract:
A multi-layer interconnect structure of alternating dielectric (e. g. , polyimide) and metal (e. g. , copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.
Manufacturing Fiber Arrays
US Patent:
2003008, May 1, 2003
Filed:
Aug 16, 2002
Appl. No.:
10/222119
Inventors:
David Volfson - Worcester MA, US
Geoffrey Kaiser - Groton MA, US
Patrick Tan - Wellesley MA, US
John Berg - Franklin MA, US
Geoffrey Kaiser - Groton MA, US
Patrick Tan - Wellesley MA, US
John Berg - Franklin MA, US
International Classification:
B29D011/00
US Classification:
216/024000
Abstract:
A method of forming fiber arrays includes using a base substrate to form an alignment pattern, holding a fiber fixed with reference to the pattern, and, while the fiber is held fixed, bonding a cap to the fiber, the cap being of a material having a different coefficient of thermal expansion than the base substrate. The base substrate can be an etched silicon chip and the cap can be of a fused silicon material. The method provides one and two dimensional arrays of fibers, the fiber aligning structures of the arrays having coefficients of thermal expansion selected to match those of connecting components. A fiber array made by the method includes a pair of substrates, a fiber sandwiched between the substrates, and a molded material holding the fiber in a predetermined alignment with respect to a pattern preformed in the molded material.