DAVID THOMSON
Pilots at Plumas Ct, Fremont, CA

License number
California A5154537
Issued Date
Nov 2015
Expiration Date
Nov 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
39573 Plumas Ct, Fremont, CA 94538

Organization information

See more information about DAVID THOMSON at bizstanding.com

David Thomson MD

3161 Walnut Ave, Fremont, CA 94538

Industry:
Family Doctor
Phone:
(510) 796-1000 (Phone)
David Gwynn Thomson

Professional information

David Thomson Photo 1

Four Current Transistor Temperature Sensor And Method

US Patent:
6554469, Apr 29, 2003
Filed:
Apr 17, 2001
Appl. No.:
09/837816
Inventors:
David Thomson - Fremont CA
John Blake - Limerick, IE
Lorcan Mac Manus - Co. Kildare, IE
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 3500
US Classification:
374178, 327512, 327513, 374163, 374183
Abstract:
A four current transistor temperature sensor comprises a p-n junction, preferably the base-emitter junction of a bipolar transistor, which is driven with four different currents in a predetermined sequence. Each of the four currents induces a respective base-emitter voltage, which is measured. The temperature of the transistor is calculated based on the values of the four driving currents and the four measured base-emitter voltages. The four driving currents (I , I , I and I ) are preferably arranged such that I *I , I *I , I /I =A and I /I =A, where A is a predetermined current ratio. I and I produce respective base-emitter voltages which are subtracted from each other to produce V , and I and I produce respective base-emitter voltages which are subtracted from each other to produce V. When so arranged, the difference between V and V is entirely due to the effect of series base and emitter resistances r and r. Therefore, the V -V value provides a correction factor which enables temperature measurement errors due to r and r to be eliminated.


David Thomson Photo 2

Voltage Source Circuit With Selectable Temperature Independent And Temperature Dependent Voltage Outputs

US Patent:
7112948, Sep 26, 2006
Filed:
Jan 27, 2005
Appl. No.:
11/045885
Inventors:
Michael P. Daly - Wicklow, IE
Evaldo M. Miranda - Saratoga CA, US
David Thomson - Fremont CA, US
A. Paul Brokaw - Tucson AZ, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G05F 3/16, G05F 1/10, H03F 3/45
US Classification:
323316, 323317, 327538
Abstract:
A voltage source includes first and second pn junctions which conduct the outputs of respective current sources to establish respective base-emitter voltages Vand Vat respective nodes; Vand Vcan each be generated with a current I or a current N*I. An amplifier A has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. Switches are connected between A's inverting input and A's output, between the third node and A's output, and between the third node and a circuit common point. A control circuit operates the switches and current sources during first and second operating phases to selectively produce a temperature independent output voltage or a temperature dependent output voltage.


David Thomson Photo 3

Analog-To-Digital Converter With Sigma-Delta Duty Cycle Encoded Output

US Patent:
5559514, Sep 24, 1996
Filed:
Aug 9, 1994
Appl. No.:
8/287664
Inventors:
David Thomson - Fremont CA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03M 302, H03M 160
US Classification:
341143
Abstract:
An analog-to-digital converter employs a sigma-delta modulator that produces a pulsed output with an average duty cycle that varies with an analog input to the modulator. A counter averages the modulator's output duty cycle, and feeds the averaged information onto a one-line transmission circuit for delivery to a remote location. Both the sigma-delta modulator and the counter are synchronized to the same local clock, so that the counter's duty cycle remains substantially constant even if the clock frequency varies. This allows for a simple clock configuration that can be integrated along with the sigma-delta modulator and counter on a single IC chip of reasonable size. When used for temperature sensing, the counter's output duty cycle provides an indication of the locally sensed temperature, independent of temperature-induced variations in the clock frequency.


David Thomson Photo 4

Ic Monitoring Chip And A Method For Monitoring Temperature Of A Component In A Computer

US Patent:
6169442, Jan 2, 2001
Filed:
Apr 13, 1999
Appl. No.:
9/291409
Inventors:
Patrick Meehan - Pallaskenry, IE
John Blake - Raheen, IE
David Thomson - Fremont CA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 342
US Classification:
327513
Abstract:
An IC monitoring chip (10) for remotely monitoring the output of a thermal diode (5) formed in the substrate of a CPU (2) for monitoring the temperature of a thermal plate (3) of the CPU (2) comprises a signal conditioning circuit (12) which relays the output from the diode (5) to an analog-to-digital converter (14), which in turns outputs a two's compliment signal to an adder (22). The adder (22) adds the two's compliment signal to a temperature offset value stored in a temperature offset register (17), which compensates for the temperature difference between the diode (5) and the thermal plate (3). Comparators (24) and (25) compare the output from the adder (22) with upper and lower predetermined temperature limits in upper and lower limit registers (19) and (20) for determining the temperature of the thermal plate (3). The temperature offset value is stored in ROM (35) of the computer (1) and is written to the register (17) each time the computer (1) is powered up. The IC chip (10) operates independently of the CPU (2).


David Thomson Photo 5

Cascaded Resistance Ladder Attenuator Network

US Patent:
5339021, Aug 16, 1994
Filed:
Feb 24, 1993
Appl. No.:
8/021804
Inventors:
David Thomson - Fremont CA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03H 726
US Classification:
323354
Abstract:
A voltage attenuation network includes one or more cascaded resistor ladder stages, with decremented voltage taps provided at successive cascaded steps within each stage. Each stage includes a termination step having a resistance value Ri equal to the stage input impedance, series step resistors with resistance values Ri(1-A)/A and shunt step resistors with resistance values Ri/(1-A), where A is a step-to-step voltage attenuation factor. The input resistances of each step within a given stage are substantially equal, eliminating the need for output buffers at the step taps. A pair of switches are provided for each step, including an output switch connected between the step input node and a common output line, and a shunt switch connected in series with the shunt resistor for that step. Only one output switch is closed at a time, and only the corresponding shunt switch for the same step is opened. Multiple stages can be cascaded to provide a progressively finer voltage decremention, with the input impedance for each stage equal to the shunt resistance values for the preceding stage.


David Thomson Photo 6

Tri-State Input Detection Circuit

US Patent:
6133753, Oct 17, 2000
Filed:
Nov 25, 1998
Appl. No.:
9/200316
Inventors:
David Thomson - Fremont CA
Paul Sheridan - Monaleen, IE
John Cleary - Fermoy, IE
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 1900, H03K 1902
US Classification:
326 56
Abstract:
A tri-state input detection circuit produces two binary outputs that indicate whether a tri-state input signal is high, low, or in a hi-impedance state. A pair of transistors conduct a current in response to a tri-state signal presented at an input node. Circuitry is provided to pull the input node to a known voltage when the input signal is in its hi-Z state. The transistors are series-connected to respective current sources, with the junctions between the transistors and their current sources forming the circuit's binary outputs. The output impedances of the current sources are made less than those of their respective transistors, so that when turned on by the input signal, a transistor pulls its associated output high or low. The circuit produces a unique binary output for each of the three input signal states. In a preferred embodiment, sampling pulses briefly activate the circuit, and downstream circuitry latches the circuit's outputs, reducing current consumption to zero except during the sampling period.


David Thomson Photo 7

Watchdog Circuit Employing Minimum And Maximum Interval Detectors

US Patent:
5627867, May 6, 1997
Filed:
Feb 29, 1996
Appl. No.:
8/610156
Inventors:
David Thomson - Fremont CA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G07C 302
US Classification:
377 16
Abstract:
A watchdog circuit accepts an output signal from a monitored circuit such as a microprocessor to determine whether the monitored circuit is operating appropriately or has incurred an error. The monitored circuit must periodically assert the output signal to prevent the watchdog circuit, which imposes both upper and lower frequency bounds on the assertion of this signal, from "timing out" and setting a watchdog error alarm. The watchdog circuit may be combined with other circuits, such as power on reset, battery back-up switching, etc. , within a microprocessor supervisory circuit.


David Thomson Photo 8

Programmable Fuse State Determination System And Method

US Patent:
7030641, Apr 18, 2006
Filed:
Sep 17, 2004
Appl. No.:
10/943370
Inventors:
Andrew T. K. Tang - San Jose CA, US
Trey Roessig - Fremont CA, US
David Thomson - Fremont CA, US
Jonathan Audy - Los Gatos CA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G01R 31/26
US Classification:
324765
Abstract:
A programmable fuse state determination system and method provide a fuse current through a programmed fuse which produces a voltage that varies with the fuse's resistance. The voltage is compared with a threshold voltage to indicate whether the fuse is blown or intact. The invention employs ‘normal’ and ‘test’ modes, in which the relationship between the fuse's resistance and the threshold voltage differ, such that a higher fuse resistance is required for the fuse to be determined blown in the ‘test’ mode than in the ‘normal’ mode.


David Thomson Photo 9

Serial Digital Communication System And Method

US Patent:
7266077, Sep 4, 2007
Filed:
Feb 10, 2004
Appl. No.:
10/776944
Inventors:
Michael P. Daly - Wicklow, IE
David Thomson - Fremont CA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H04J 7/00
US Classification:
370212, 375238, 332109
Abstract:
A serial digital communication system includes a master device and a plurality of slave devices connected serially between the master device's output and input—thereby forming a closed chain. Each slave device transmits a predetermined number of PWM pulses to the device following it in the chain upon receipt of an end-of-transmission (EOT) signal from the device preceding it in the chain, and transmits an EOT signal when the transmission of its PWM pulses is completed. The master device transmits an EOT signal to initiate the transmission of PWM pulses from each slave device. Each slave device passively buffers PWM pulses received from the preceding device, such that PWM pulses are transmitted in one direction sequentially to the input of the master device via the intervening slave device.


David Thomson Photo 10

Ratio Correction Circuit And Method For Comparison Of Proportional To Absolute Temperature Signals To Bandgap-Based Signals

US Patent:
5933045, Aug 3, 1999
Filed:
Feb 10, 1997
Appl. No.:
8/798518
Inventors:
Jonathan Audy - San Jose CA
A. Paul Brokaw - Burlington MA
Evaldo Miranda - San Jose CA
David Thomson - Fremont CA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G05F 110, G05F 316
US Classification:
327513
Abstract:
A comparison system compares a voltage which is proportional to absolute temperature S. sub. p to one which is equal to the sum of a conventional, uncorrected, bandgap cell voltage VBG and a proportional to absolute temperature voltage CT. The addition of CT to the uncorrected bandgap signal value yields a signal of the form Sp/(VBG+CT), which exhibits improved linearity over a signal of the form Sp/VBG, where VBG includes a Tln(T) term.