DAVID S DOUGLAS
Social Work in Boston, MA
License number
Massachusetts 2015597
Issued Date
Apr 25, 1988
Expiration Date
Oct 1, 1990
Type
Licensed Certified Social Worker
Address
Address
Boston, MA 02130
Professional information
Director Of Manufacturing At Charm Sciences
Position:
Director of Manufacturing at Charm Sciences
Location:
Greater Boston Area
Industry:
Biotechnology
Work:
Charm Sciences
since Jan 2004
-
Director of Manufacturing
Charm Sciences, Inc.
1998 - 2003
-
Raw Materials Manager
Charm Sciences, Inc.
1995 - 1998
-
Production Supervisor
Harvard University School of Public Health
Jan 1993 - Sep 1993
-
Lab Technician
Education:
Boston University 1989 - 1993
Bachelor's degree, Biology, General
Bachelor's degree, Biology, General
Skills:
Inventory Management, Laboratory, Organic Synthesis, Negotiation, Sales, Microsoft Excel, GMP, Microsoft Office, ERP, CAPA, Fermentations, FPLC, Affinity Chromatography, AKTA, Binding Assays, Radioligand Binding, Receptor Binding Assays, Luciferase Assay
Interests:
fishing
David Douglas
Location:
Greater Boston Area
Industry:
Computer Hardware
Skills:
Android, Sustainability, Start-ups, Enterprise Software, Cloud Computing, Change Management, Architecture, Product Management, Strategic Partnerships, Management, Vendor Management, SaaS, Networking
Method And Apparatus For Interfacing Bit-Serial Parallel Processors To A Coprocessor
US Patent:
5148547, Sep 15, 1992
Filed:
May 17, 1991
Appl. No.:
7/704688
Inventors:
Brewster A. Kahle - Somerville MA
David C. Douglas - Boston MA
Alexander Vasilevsky - Watertown MA
David P. Christman - Newport VT
Shaw W. Yang - Waltham MA
Kenneth W. Crouch - Cambridge MA
David C. Douglas - Boston MA
Alexander Vasilevsky - Watertown MA
David P. Christman - Newport VT
Shaw W. Yang - Waltham MA
Kenneth W. Crouch - Cambridge MA
Assignee:
Thinking Machines Corporation - Cambridge MA
International Classification:
G06F 1516
US Classification:
395800
Abstract:
A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors. In accordance with a preferred embodiment of the invention, three or more transposers are used in connection with each word-oriented processor so as to provide a pipelining capability that significantly enhances processing speeds.