David Preston Porter
Accountancy in Boise, ID
License number
Utah 129386-2601
Issued Date
Jan 1, 1910
Expiration Date
Aug 31, 1982
Category
Accountancy
Type
Certified Public Accountant
Address
Address
Boise, ID
Professional information
Owner, Advocate Financial, Llc
Position:
President and Managing Director at D & S Homes, Inc. and Advocate Financial, LLC
Location:
Boise, Idaho Area
Industry:
Real Estate
Work:
D & S Homes, Inc. and Advocate Financial, LLC
since Jan 1995
-
President and Managing Director
Education:
Brigham Young University
Masters Degree, Business and Accounting
Masters Degree, Business and Accounting
Circuit, Biasing Scheme And Fabrication Method For Diode Accessed Cross-Point Resistive Memory Array
US Patent:
2013001, Jan 10, 2013
Filed:
Sep 13, 2012
Appl. No.:
13/614513
Inventors:
Jun Liu - Boise ID, US
David Porter - Boise ID, US
David Porter - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/02
US Classification:
438382, 257E21004
Abstract:
Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations.
Circuit, Biasing Scheme And Fabrication Method For Diode Accessed Cross-Point Resistive Memory Array
US Patent:
8335100, Dec 18, 2012
Filed:
Jun 14, 2007
Appl. No.:
11/812004
Inventors:
Jun Liu - Boise ID, US
David Porter - Boise ID, US
David Porter - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/00
US Classification:
365148, 365163, 365171, 365173, 365175, 365243
Abstract:
Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations.