DAVID MONEY HARRIS
Pilots at Euclid Ave, Upland, CA
License number
California A4026196
Issued Date
Aug 2016
Expiration Date
Aug 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
1320 N Euclid Ave, Upland, CA 91786
Professional information
Multiplicand Shifting In A Linear Systolic Array Modular Multiplier
US Patent:
7693925, Apr 6, 2010
Filed:
Sep 30, 2005
Appl. No.:
11/242573
Inventors:
Sanu K. Mathew - Hillsboro OR, US
David L. Harris - Upland CA, US
Ram Krishnamurthy - Portland OR, US
David L. Harris - Upland CA, US
Ram Krishnamurthy - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/72
US Classification:
708491
Abstract:
Embodiments of apparatuses and methods for multiplicand shifting in a linear systolic array modular multiplier are disclosed. In one embodiment, an apparatus includes two processing elements of a linear systolic array. One processing element includes multiplication logic, multiplicand shift logic, an adder, modulus logic, and modulus shift logic. The multiplication logic is to multiply a word of the multiplicand and a bit of the multiplier to generate a product. The multiplicand shift logic is to shift the word of the multiplicand. The adder is to add the product to a first running sum to generate a second running sum. The modulus logic is to conditionally add a word of a modulus and the second running sum. The modulus shift logic is to shift the word of the modulus. The next processing element includes logic to multiply the shifted word of the multiplicand and the next bit of the multiplier.
Dual Edge Triggered Flip Flops
US Patent:
7671653, Mar 2, 2010
Filed:
Sep 28, 2007
Appl. No.:
11/864504
Inventors:
David Money Harris - Upland CA, US
Scott M. Fairbanks - Mountain View CA, US
Scott M. Fairbanks - Mountain View CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 3/00
US Classification:
327218, 327212
Abstract:
An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.
Multiple-Output Static Logic
US Patent:
7570081, Aug 4, 2009
Filed:
Aug 30, 2006
Appl. No.:
11/513605
Inventors:
David Money Harris - Upland CA, US
Chih-Kong Yang - Pacific Palisades CA, US
Chih-Kong Yang - Pacific Palisades CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 19/20, H03K 19/094
US Classification:
326121, 326119
Abstract:
An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes building multiple-output static NAND gates that compute the subfunctions of three or more inputs and building multiple-output static NOR gates that compute the subfunctions of two or more inputs. The approach also includes building multiple-output static XOR-XNOR gates that are capable of computing two-input XOR, three-input XOR, two-input XNOR, and three-input XNOR, and building multiple-output static Propagate-Generate (PG) compound gates. The approach further includes building carry propagate adders, priority encoders, binary-to-thermometers, decoders, etc. that are capable of using the multiple-output static gates embodied in the present invention.