David M. Weber
Engineers at Range Vw Rd, Woodmoor, CO

6185620, Feb 6, 2001

Apr 3, 1998

9/054849

David M. Weber - Monument CO
Timothy E. Hoglund - Colorado Springs CO
Stephen M. Johnson - Colorado Springs CO
John M. Adams - Colorado Springs CO
Mark A. Reber - Alpharetta GA

LSI Logic Corporation

G06F 1100, G06F 946, H04Q 1104

709230

A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received.

6747984, Jun 8, 2004

Dec 18, 1998

09/216401

Timothy E. Hoglund - Colorado Springs CO
Stephen M. Johnson - Colorado Springs CO
David M. Weber - Monument CO
John M. Adams - Colorado Springs CO
Mark A. Reber - Alpharetta GA

LSI Logic Corporation - Milpitas CA

H04L 1254

370428, 370400, 370412, 370231, 709215

A method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.

6570853, May 27, 2003

Oct 4, 2000

09/679506

Stephen M. Johnson - Colorado Springs CO
Timothy E. Hoglund - Colorado Springs CO
David M. Weber - Monument CO
John M. Adams - Colorado Springs CO
Mark A. Reber - Alpharetta GA

LSI Logic Corporation - Milpitas CA

H04L 1228

370236, 370412, 3703952, 370400

A method and apparatus in a source node for transmitting data to a target node. Responsive to a request to transmit data to the target node, a determination is made as to whether a selected period of time has passed without data transmitted from the source node being received by the target node. Responsive to detecting the selected period of time has passed without data transmitted from the source node being received by the target node, a determination is made as to whether space is available in the target node to receive the data. Responsive to a determination that space is unavailable in the target node, generating an indication that the target node is blocked is generated.

5761424, Jun 2, 1998

Dec 29, 1995

8/580955

John M. Adams - Colorado Springs CO
Timothy E. Hoglund - Colorado Springs CO
Stephen M. Johnson - Colorado Springs CO
Mark A. Reber - Colorado Springs CO
David M. Weber - Monument CO

Symbios, Inc. - Fort Collins CO

G06F 1516

39520047

A method and associated apparatus for automating the filtration and generation of information in a packetized communication system. A filtration table includes entries used in recognizing a valid packet received at a node in a communication system. A mask field in each entry is applied to appropriate fields in the packet (e. g. the ordered set as applied to Fibre Channel communication systems) to determine the validity of the packet with regard to the receiving node. Rules in a field of each entry further qualify the recognition of a received packet (e. g. ordered set) by testing the reception of the packet against other logical rules. Action fields in each record permit definition of actions to be invoked automatically (e. g. automatic adjustment of fill transmissions in Fibre Channel applications) in response to receipt and recognition of a particular packet. The set of packets recognized by the receiving node may be modified by adding, deleting, or modifying the entries in the filtration table.

6134617, Oct 17, 2000

Apr 3, 1998

9/054850

David M. Weber - Monument CO

LSI Logic Corporation - Milpitas CA

G06F 1300

710105

A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on chip processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received.

6274395, Aug 14, 2001

Dec 23, 1999

9/471842

David M. Weber - Monument CO

LSI Logic Corporation - Milpitas CA

G01R 3126

438 14

A method of fabricating a semiconductor wafer includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. In addition, the method includes the step of storing the test data obtained during the testing step in the memory device. Moreover, the method includes the step of retrieving the test data from the memory device. Yet further, the method includes the step of operating a packaging apparatus so as to package a first die of the number of die based on the test data. A semiconductor wafer is also disclosed.

5781769, Jul 14, 1998

Dec 29, 1995

8/580110

David M. Weber - Monument CO

Symbios, Inc. - Fort Collins CO

G06F 104

395557

A method and associated apparatus for using a content addressable memory (CAM) to process timed events in a process control application. A time value field in each CAM entry identifies the time at which a corresponding event is to be processed. An event identifier field in each CAM entry identifies the event to be processed. A time value generator applies signals indicative of a time value to the CAM. The CAM returns as data on its output signal paths any entries whose time value fields correspond to the applied time value signals. The event identifier field applied to the output signal paths of the CAM is then applied to the process controller to identify an event to be processed. The methods and apparatus of the present invention are applicable, for example, in communication controller devices wherein a protocol requires timed event processing for standardized communications (e. g. , Fibre Channel or FDDI).

6097775, Aug 1, 2000

Feb 17, 1998

9/024919

David M. Weber - Monument CO

LSI Logic Corporation - Milpitas CA

H04L 700, H04L 1310, G06F 9445

375354

A method and apparatus of a synchronizer circuit for transferring signals between two clock domains in which a first synchronizer unit and a second synchronizer unit form a hand-shaking protocol. In particular, an input event from a source clock domain is captured in an input unit and a first signal is asserted indicating that the input signal is to be transferred to a target clock domain. This first signal is synchronized to the clock signal in the target clock domain at the first synchronizer unit, causing assertion of a second signal. The second signal is coupled to an output unit which generates an output event signal for a single clock period.

6246278, Jun 12, 2001

Dec 22, 1995

8/580036

Michael B. Anderson - Colorado Springs CO
Kenneth C. Schmitt - Colorado Springs CO
David M. Weber - Monument CO

LSI Logic Corporation - Milpitas CA

G06F 104

327295

A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

7818461, Oct 19, 2010

Apr 28, 2003

10/424408

David M. Weber - Monument CO, US

LSI Corporation - Milpitas CA

G06F 15/16, G06F 15/173

709251, 709226

Systems and methods for allocating assets to a plurality of devices are presented. In one embodiment, devices may be communicatively connected to one another through a device loop. Each device may be configured for determining a portion of an asset that it will use. A controller may also be communicatively connected to the communication medium and configured for determining a capacity of the asset. The controller may transfer control information to the devices so as to allocate the asset to the devices based on the capacity of that asset. In another embodiment, each of the devices may be communicatively connected directly to the controller rather than to one another.