DAVID M KNAPP
Cosmetology in San Jose, CA

6782511, Aug 24, 2004

May 25, 2000

09/579825

Elof Frank - Sunnyvale CA
Bernd Braune - Menlo Park CA
David Knapp - San Jose CA
Pradeep Fernandes - San Jose CA
Hans-Joachim Schmidt - Munich, DE

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 1, 716 18, 716 3, 716 9, 716 10

A business-to-business application service provider includes an Internet website and webserver with EDA-on-demand solutions for system-on-a-chip designers. Such website allows electronic designs in hardware description language to be uploaded into a front-end EDA design environment. A behavioral model simulation tool hosted privately on the webserver tests and validates the design. Such tool executes only in the secure environment of the business-to-business application service provider. The validated solution is then downloaded back over the Internet for a pay-per-use fee to the customer, and in a form ready to be placed and routed by a back-end EDA tool. Such validated design solutions are also downloadable to others in exchange for other designs, or available in technology libraries. The intellectual property created can be re-used, sold, shared, exchanged, and otherwise distributed efficiently and easily from a central for-profit clearinghouse.

6470486, Oct 22, 2002

May 17, 2000

09/574693

David Knapp - San Jose CA

Get2Chip - San Jose CA

G06F 1750

716 18, 716 10, 716 8, 716 7, 716 6, 716 3, 716 2

A delay-optimizing technology-mapping process for an electronic design automation system selects the best combination of library devices to use in a forward and a backward sweep of circuit trees representing a design. A technology selection process in an electronic design automation-system comprises the steps of partitioning an original circuit design into a set of corresponding logic trees. Then, ordering the set of corresponding logic trees into an ordered linear list such that each tree-T that drives another ordered tree precedes the other ordered tree, and such that each ordered tree that drives the tree-T precedes the tree-T. Next, sweeping forward in the ordered linear list while computing a set of Pareto-optimal load/arrival curves for each of a plurality of net nodes that match a technology-library element. And, sweeping backward in the ordered linear list while using the set of Pareto-optimal load/arrival curves for each of the net nodes and a capacitive load to select a best one of the technology-library elements with a shortest signal arrival time. Wherein, only those net nodes that correspond to gate inputs are considered, and any capacitive loads are predetermined.

6516453, Feb 4, 2003

May 17, 2000

09/574572

David Knapp - San Jose CA

Get2Chip - San Jose CA

H06F 1750

716 6, 364489, 364490, 364491, 395558

A design-timing-determination process for an electronic design automation system approximates the timing of a whole design quickly and on-the-fly. Such allows a scheduling system to construct operation schedules that are ultimately realizable. A timing analysis is applied each time an individual operation is scheduled, and may be called many times to get a single operation scheduled. A graph representing combinational logic is partitioned into a collection of logic trees with nodes that represent gates and terminals, and arcs that represent connections. A compacted model of each logic tree is constructed by replacing them with equivalent trees having no interior nodes. The timing of the original circuit is analyzed along each path from the leaves to the roots. A propagation delay for each path is determined, and such is annotated onto each corresponding arc of the simplified tree. Any dependency of the propagation delay in the original circuit on the slew rate of their input signals is annotated onto the corresponding leaf of the simplified tree.

RE40925, Sep 29, 2009

Jun 8, 2000

09/590584

Tai A. Ly - San Jose CA, US
David W. Knapp - San Jose CA, US
Ronald A. Miller - Cupertino CA, US
Donald B. Macmillen - Redwood City CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 18, 716 1

A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.